Intel IXP12xx manual Frame and PDU Length versus IP Packet Length

Page 5

Version 1.0, 4/10/02

The result is that ATM is significantly more efficient that Ethernet in terms of Mbps for carrying very small PDUs. Every Mbps of single-cell-PDUs on the ATM link requires (84/55) Mbps on the matching Ethernet link(s).

176

 

 

 

 

 

 

 

160

 

 

 

 

 

 

 

144

 

 

 

 

 

 

 

128

 

 

 

 

 

 

 

112

 

 

 

 

 

 

 

96

 

 

 

 

 

 

 

80

 

 

 

 

 

 

 

64

 

 

 

 

 

 

 

48

 

 

 

 

 

 

 

32

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

0

20

40

60

80

100

120

140

 

 

 

IP P a c ke t Le ngth [Byte s]

 

 

 

Ethernet Frame Bytes AAL5 PDU Length

Figure 2 – Frame and PDU Length versus IP Packet Length

1000

900

800

700

600

500

400

300

200

100

0

0

100

200

300

400

500

600

700

800

900

1000

1100

1200

1300

1400

1500

IP P a c ke t Le ngth [Byte s]

OC- 12 Input OC- 3 Input

Figure 3 – Expected Ethernet Transmit Bandwidth

Page 5 of 17

Image 5
Contents IXP12xx ATM OC12/Ethernet IP Router Example Design Version 1.0, 4/10/02 Alternate Dram Timing OverviewMeasurement Environment Single Cell PDU Workload KEY Workloads & Approaches to Testing the Example DesignProtocol Performance of IP over ATM vs. Ethernet Frame and PDU Length versus IP Packet Length Cycle and Instruction Budgets Multiple Cells/PDU WorkloadCycle Budgets to support Line Rates Cycles/cellCells/PDU Virtual Circuits Cycles/Cell Cycles/cell -7E Usec/frame = 1559 cycles/frameSimulated 29-byte packet performance1 Simulation Measurement Procedure and ResultsHardware Measurement Results Hardware Measurement Procedure and ResultsSimulated 40-byte and 1500-byte packet performance2 Hardware 29-byte packet performance Single-cell/PDU Performance using 133MHZ Dram138 142 144 Hardware 40-byte packet performance9.5 88,300517 Hardware 1500-byte packet performance518 Ethernet Queue to Core Throughput Queue to Core Measurement TechniqueATM Queue to Core Throughput Microengine Register and Microstore Headroom Resource Utilization and Headroom AnalysisSram Capacity Scratchpad RAM CapacitySram and Sdram Bandwidth Sdram CapacityBuffer Allocation in Dram Appendix