Intel UPI-C42, UPI-L42 specifications DIP Pin, Configuration

UPI-C42/UPI-L42

UNIVERSAL PERIPHERAL INTERFACE

CHMOS 8-BIT SLAVE MICROCONTROLLER

YPin, Software and Architecturally Compatible with all UPI-41 and UPI-42 Products

YLow Voltage Operation with the UPI- L42

— Full 3.3V Support

YHardware A20 Gate Support

YSuspend Power Down Mode

YSecurity Bit Code Protection Support

Y8-Bit CPU plus ROM/OTP EPROM, RAM, I/O, Timer/Counter and Clock in a Single Package

Y4096 x 8 ROM/OTP, 256 x 8 RAM 8-Bit Timer/Counter, 18 Programmable I/O Pins

YDMA, Interrupt, or Polled Operation Supported

YOne 8-Bit Status and Two Data Registers for Asynchronous Slave-to- Master Interface

YFully Compatible with all Intel and Most Other Microprocessor Families

YInterchangeable ROM and OTP EPROM Versions

YExpandable I/O

YSync Mode Available

YOver 90 Instructions: 70% Single Byte

YQuick Pulse Programming Algorithm

— Fast OTP Programming

YAvailable in 40-Lead Plastic, 44-Lead Plastic Leaded Chip Carrier, and 44-Lead Quad Flat Pack Packages

(See Packaging Spec., Order Ý240800, Package Type P, N, and S)

The UPI-C42 is an enhanced CHMOS version of the industry standard Intel UPI-42 family. It is fabricated on Intel’s CHMOS III-E process. The UPI-C42 is pin, software, and architecturally compatible with the NMOS UPI family. The UPI-C42 has all of the same features of the NMOS family plus a larger user programmable memory array (4K), hardware A20 gate support, and lower power consumption inherent to a CHMOS product.

The UPI-L42 offers the same functionality and socket compatibility as the UPI-C42 as well as providing low voltage 3.3V operation.

The UPI-C42 is essentially a ‘‘slave’’ microcontroller, or a microcontroller with a slave interface included on the chip. Interface registers are included to enable the UPI device to function as a slave peripheral controller in the MCS Modules and iAPX family, as well as other 8-, 16-, and 32-bit systems.

To allow full user flexibility, the program memory is available in ROM and One-Time Programmable EPROM (OTP).

290414 – 1
Figure 1. DIP Pin	290414 – 2	290414 – 3
		Figure 3. QFP Pin Configuration
Configuration	Figure 2. PLCC Pin Configuration

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COPYRIGHT ' INTEL CORPORATION, 1996 December 1995 Order Number: 290414-003