Intel UPI-L42, UPI-C42 specifications Waveforms, Combination PROGRAM/VERIFY Mode, Verify Mode

Page 22

WAVEFORMS (Continued)

290414 – 25

NOTES:

1.A0 must be held low (0V) during program/verify modes.

2.For VIH, VIH1, VIL, VIL1, VDDH, and VDDL, please consult the D.C. Characteristics Table.

3.When programming the 87C42, a 0.1 mF capacitor is required across VDD and ground to suppress spurious voltage

transients which can damage the device.

290414 – 26

NOTES:

1.PROG must float if EA is low.

2.PROG must float or e 5V when EA is high.

3.P10 – P17 e 5V or must float.

4.P24 – P27 e 5V or must float.

5.A0 must be held low during programming/verify modes.

Image 22

Contents Configuration DIP PinUPI-C42/UPI-L42 Pin DescriptionBlock Diagram Intel 82C42 UPI-C42 Low power Chmos version of the UPI-42UPI-C42/L42 Product Selection Guide UPI-L42 The low voltage 3.3V version of the UPI-C42Bits of Status UPI-42 Compatible FeaturesIBF OBF UPI-C42 Features Program Memory Bank SwitchInterrupt Routines Suspend Mode Summary SuspendRDÝ, WRÝ NEW UPI-C42 InstructionsNew Instructions XTAL1, XTAL2BUS Programming and Verifying the UPI-C42Xtal ProgSecurity BIT Quick-Pulse Programming AlgorithmVerify Security BIT PROGRAMMING/ VerificationSync Mode Signature ModeVerification Access Code Sync Mode Timing Diagrams ApplicationsUPI-C42-8243 Keyboard Scanner UPI-C42 80-Column Matrix Printer InterfaceAbsolute Maximum Ratings XTAL2, ResetRESET, SS UPI-C42 UPI-L42DC Characteristics DBB Read AC CharacteristicsDBB Write AC Characteristics Port AC Characteristics DMAClock AC CHARACTERISTICS-PROGRAMMING UPI-C42 and UPI-L42 AC Testing INPUT/OUTPUT Waveform AC Testing Load CircuitLC Oscillator Mode Crystal Oscillator Mode Driving from AN External SourceWrite OPERATION-DATA BUS Buffer Register WaveformsRead OPERATION-DATA BUS Buffer Register Clock TimingVerify Mode Combination PROGRAM/VERIFY ModeWaveforms DMA Port Timing During External Access EAPort UPI Instruction Set AccumulatorRevision Summary Jmpp @A