Intel UPI-C42, UPI-L42 specifications Dma, Port Timing During External Access EA

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UPI-C42/UPI-L42

WAVEFORMS (Continued)

DMA

290414 – 27

PORT 2

290414 – 28

PORT TIMING DURING EXTERNAL ACCESS (EA)

290414 – 29

On the Rising Edge of SYNC and EA is Enabled, Port Data is Valid and can be Strobed. On the Trailing Edge of Sync the Program Counter Contents are Available.

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Contents DIP Pin ConfigurationPin Description UPI-C42/UPI-L42Block Diagram UPI-L42 The low voltage 3.3V version of the UPI-C42 UPI-C42 Low power Chmos version of the UPI-42UPI-C42/L42 Product Selection Guide Intel 82C42IBF OBF UPI-42 Compatible FeaturesBits of Status Interrupt Routines Program Memory Bank SwitchUPI-C42 Features Suspend Suspend Mode SummaryXTAL1, XTAL2 NEW UPI-C42 InstructionsNew Instructions RDÝ, WRÝProg Programming and Verifying the UPI-C42Xtal BUSSecurity BIT PROGRAMMING/ Verification Quick-Pulse Programming AlgorithmVerify Security BITVerification Signature ModeSync Mode Access Code Applications Sync Mode Timing DiagramsUPI-C42 80-Column Matrix Printer Interface UPI-C42-8243 Keyboard ScannerUPI-C42 UPI-L42 XTAL2, ResetRESET, SS Absolute Maximum RatingsDC Characteristics DBB Write AC CharacteristicsDBB Read Clock AC Characteristics DMAAC Characteristics Port AC Testing INPUT/OUTPUT Waveform AC Testing Load Circuit AC CHARACTERISTICS-PROGRAMMING UPI-C42 and UPI-L42Driving from AN External Source LC Oscillator Mode Crystal Oscillator ModeClock Timing WaveformsRead OPERATION-DATA BUS Buffer Register Write OPERATION-DATA BUS Buffer RegisterWaveforms Combination PROGRAM/VERIFY ModeVerify Mode Port Port Timing During External Access EADMA Accumulator UPI Instruction SetJmpp @A Revision Summary