Intel 317443-001US Glossary of Terms and Acronyms, Aggressor, Anti-etch, Bus Agent, Crosstalk

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1.3Glossary of Terms and Acronyms

About This Manual—Intel®945GME Express Chipset

1.3Glossary of Terms and Acronyms

This section defines conventions and terminology used throughout this document.

Aggressor

A network that transmits a coupled signal to another network.

Anti-etch

Any plane-split, void or cutout in a VCC or GND plane.

Assisted Gunning Transceiver Logic+

The front-side bus uses a bus technology called AGTL+, or Assisted Gunning Transceiver Logic. AGTL+ buffers are open- drain, and require pull-up resistors to provide the high logic level and termination. AGTL+ output buffers differ from GTL+ buffers with the addition of an active pMOS pull-up transistor to assist the pull-up resistors during the first clock of a low-to-high voltage transition.

Asynchronous GTL+ The processor does not utilize CMOS voltage levels on any signals that connect to the processor. As a result, legacy input signals such as A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/ NMI, PWRGOOD, SMI#, SLP#, and STPCLK# utilize GTL+ input buffers. Legacy output signals (FERR# and IERR#) and non- AGTL+ signals (THERMTRIP# and PROCHOT#) also utilize GTL+ output buffers. All of these signals follow the same DC requirements as AGTL+ signals, however the outputs are not actively driven high (during a logical 0 to 1 transition) by the processor (the major difference between GTL+ and AGTL+). These signals do not have setup or hold time specifications in relation to BCLK[1:0], and are therefore referred to as “Asynchronous GTL+ Signals”. However, all of the Asynchronous GTL+ signals are required to be asserted for at least two BCLKs in order for the processor to recognize them.

Bus Agent

A component or group of components that, when combined,

 

represent a single load on the AGTL+ bus.

Crosstalk

The reception on a victim network of a signal imposed by

 

aggressor network(s) through inductive and capacitive coupling

 

between the networks.

 

Backward Crosstalk - Coupling that creates a signal in a

 

 

victim network that travels in the opposite direction as the

 

 

aggressor’s signal.

 

Forward Crosstalk - Coupling that creates a signal in a

 

 

victim network that travels in the same direction as the

 

 

aggressor’s signal.

 

Even Mode Crosstalk - Coupling from a signal or multiple

 

 

aggressors when all the aggressors switch in the same

 

 

direction that the victim is switching.

 

Odd Mode Crosstalk - Coupling from a signal or multiple

 

 

aggressors when all the aggressors switch in the opposite

 

 

direction that the victim is switching.

Flight Time

Flight time is a term in the timing equation that includes the

 

signal propagation delay, any effects the system has on the TCO

 

of the driver, plus any adjustments to the signal at the receiver

 

Intel® CoreTM 2 Duo processor with the Mobile Intel® 945GME Express Chipset

May 2007

Manual

Order Number: 317443-001US

9

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Contents Order Number 317443-001US Development Kit User’s ManualManual Contents Tables FiguresSATA Port 0 Data Connector Pinout J7H1 IDE Connector J7J1SATA Port 0 Power Connector Pinout J6H3 SATA Port 2 Mobile Drive Connector Pinout J8J2Intel 945GME Express Chipset-Revision History Revision History1.1 Content Overview 1.0 About This Manual1.2 Text Conventions Instructions Signal NamesNumbers Units of MeasureAggressor 1.3 Glossary of Terms and AcronymsAnti-etch Assisted Gunning Transceiver Logic+IMVP6 Inter-Symbol InterferenceMedia Expansion Card NetworkPower-Good Acronyms Sheet 1 ofAcronyms Sheet 2 of Acronyms Sheet 3 of 1.5 Product Literature 1.4 Support Options1.4.1 Electronic Support Systems 1.4.2 Additional Technical SupportRelated Documents 1.6 Related DocumentsUpdate Mobile Intel 945 Express Chipset Family Datasheet2.1.1 Intel 945GME Express Chipset Development Kit Features 2.0 Getting Started2.1 Overview Debug Features Connector Interface SummaryMiscellaneous Features Clocking2.3.1 AMI* BIOS 2.3 Software Key Features2.2 Included Hardware and Documentation 2.4 Before You Begin used when handling the board 2.5 Setting Up the Evaluation Boardcables to this product remove any hardware unless the system is unplugged2.6 Configuring the BIOS 3.1 Block Diagram Figure 1. Intel 945GME Express Chipset Development Kit Block Diagram3.0 Theory of Operation 3.2 Mechanical Form Factor 3.4 System Features and Operation3.3 Thermal Management 3.4.1 IntelR 945GME GMCH3.4.1.1 System Memory 3.4.2 ICH7-M3.4.1.2 DMI 3.4.1.3 Advanced Graphics and Display Interface3.4.2.3 On-Board LAN 3.4.2.2 PCI Slots3.4.2.4 AC’97 and High Definition Audio 3.4.2.5 ATA / Storage3.4.2.9 BIOS Firmware Hub FWH 3.4.2.6 USB Connectors3.4.2.7 LPC Super I/O SIO/LPC Slot 3.4.2.8 Serial, IrDA3.4.2.11 Clocks 3.4.3 System I/O and Connector Summary3.4.2.12 Real Time Clock 3.4.2.13 Thermal Monitoring3.4.3.1 PCI Express* Support 3.4.3.5 VGA Connector3.4.3.2 SATA Support 3.4.3.3 IDE Support3.4.3.8 Ethernet Gigabit LAN Interface connector 3.4.3.7 32 bit/33 MHz PCI Connectors3.5 Clock Generation 3.4.4 POST Code Debugger3.6 Power Management States 3.6.1 Transition to S3 3.7 Power Measurement Support3.6.2 Transition to S4 3.6.3 Transition to S5R is the value of the sense resistor typically 0.002 Ω Powered duringV is the voltage measured across the sense resistor Voltage GroupsTheory of Operation-Intel 945GME Express Chipset Intel 945GME Express Chipset-Theory of Operation 4.0 Hardware Reference 4.1 Primary FeaturesIntel 945GME Express Chipset-Hardware Reference Default SettingReference DesignatorHardware Reference-Intel 945GME Express Chipset 4.2 Back Panel Connectors 4.3 Configuration Settings Supported Configuration Jumper/Switch Settings Sheet 1 of Supported Configuration Jumper/Switch Settings Sheet 2 of 4.4 Power On and Reset Buttons 4.6 Other Headers, Slots, and Sockets 4.5 LEDs4.6.1 H8 Programming Headers Table 9. Intel 945GME Express Chipset LED Function Legend4.6.2.1 478 Pin Grid Array Micro-FCPGA Socket 4.6.2 Expansion Slots and SocketsH8 Programming Jumpers Expansion Slots and SocketsPCI Express* x16 Pinout J6C1 Sheet 1 of 4.6.2.2 PCI ExpressPCI Express* x16 Pinout J6C1 Sheet 2 of 4.6.2.3 Media Expansion Card MEC Slot Table 12. PCI Express* x16 Pinout J6C1 Sheet 3 ofMEC Slot J6C1 Sheet 1 of Intel 945GME Express Chipset-Hardware Reference MEC Slot J6C1 Sheet 2 of4.6.2.4 PCI Express MEC Slot J6C1 Sheet 3 ofPCI Express* x1 Pinout J7C1, J8C1 Sheet 1 of Table 14. PCI Express* x1 Pinout J7C1, J8C1 Sheet 2 of IDE Connector J7J1 4.6.2.5 IDE ConnectorTable 16. SATA Port 0 Data Connector Pinout J7H1 4.6.2.6 SATA PinoutTable 17. SATA Port 0 Power Connector Pinout J6H3 4.6.2.7 Fan ConnectorsTable 18. SATA Port 2 Mobile Drive Connector Pinout J8J2 Table 19. Fan Connectors J3F1 and J3C1Figure 6. Heatsink and Backplate Appendix A Heat Sink Installation InstructionsIntel 945GME Express Chipset-Heat Sink Installation Instructions Figure 7. Backplate PinsFigure 9. Squeezing Activation Arm Figure 8. Applying the Thermal GreaseFigure 10. Installing the Heatsink Figure 11. Plugging in the Fan Figure 12. Completed Assembly