Theory of
Table 6. Intel® 945GME Express Chipset Development Kit Voltage Rails (Sheet 2 of 3)
Voltage Groups | Voltage Rail | Sense Resistor | Powered during | |
System States | ||||
|
|
| ||
|
|
|
| |
| +V3.3S_PEG | R6C2 | S0 | |
|
|
|
| |
| +V3.3S_PWRGD |
| S0 | |
|
|
|
| |
| +V3.3S_SATA_P0 |
| S0 | |
|
|
|
| |
| +V3.3S_SATA_P2 |
| S0 | |
|
|
|
| |
| +V3.3S_TVDAC |
| S0 | |
|
|
|
| |
| +V3.3S_TVDAC_LDO | R4F2 | S0 | |
|
|
|
| |
| +V3.3S_TVDACA |
| S0 | |
|
|
|
| |
| +V3.3S_TVDACB |
| S0 | |
|
|
|
| |
| +V3.3S_TVDACC |
| S0 | |
|
|
|
| |
| +VCCA_TVDAC |
| S0 | |
|
|
|
| |
5V | +V5 |
| S0,S3 | |
|
|
|
| |
5V Always | +V5A |
| S0,S3,S4,S5 | |
|
|
|
| |
| +V5A_MBL | R3V4 | S0,S3,S4,S5 | |
|
|
|
| |
5V Switched | +V5S |
| S0 | |
|
|
|
| |
| +V5_PCISLT3 | R8B5 | S0 | |
|
|
|
| |
| +V5S_F_DAC |
| S0 | |
|
|
|
| |
| +V5S_IMVP6 | R1B2 | S0 | |
|
|
|
| |
| +V5S_L_DAC |
| S0 | |
|
|
|
| |
| +V5S_PATA |
| S0 | |
|
|
|
| |
| +V5S_PWRGD |
| S0 | |
|
|
|
| |
| +V5S_SATA_P0 |
| S0 | |
|
|
|
| |
| +V5S_SATA_P2 |
| S0 | |
|
|
|
| |
| +V5SB_ATXA |
| S0 | |
|
|
|
| |
| V5S_FAN |
| S0 | |
|
|
|
| |
| S0,S3,S4,S5 | |||
|
|
|
| |
| S0 | |||
|
|
|
| |
+12V SWITCHED | +V12S |
| S0 | |
|
|
|
| |
| +V12S_PATA |
| S0 | |
|
|
|
| |
| +V12S_PEG | R6N6 | S0 | |
|
|
|
| |
| +V12S_SATA_P0 |
| S0 | |
|
|
|
| |
| +V12S_SATA_P2 |
| S0 | |
|
|
|
| |
AC Power Brick | +V_BC_OUT |
| S0,S3,S4,S5 | |
|
|
|
| |
| +VAC_IN |
| S0,S3,S4,S5 | |
|
|
|
| |
| +VAC_IN_L |
| S0,S3,S4,S5 | |
|
|
|
| |
| +VCHGR_OUT |
| S0,S3,S4,S5 | |
|
|
|
| |
Battery Voltage | +VBAT |
| S0,S3,S4,S5 | |
|
|
|
| |
| +VBAT_S4 |
| S0,S3,S4,S5 | |
|
|
|
| |
| +VDC_PHASE | R1B3 | S0,S3,S4,S5 | |
|
|
|
| |
Battery Voltage Always | +VBATA |
| S0,S3,S4,S5 | |
|
|
|
|
| Intel® CoreTM 2 Duo processor with the Mobile Intel® 945GME Express Chipset |
May 2007 | Manual |
Order Number: | 33 |