IBM MiEM78P468L manual Function Description, Operational Registers, 2 R1/TCC Timer Clock Counter

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EM78P468N/EM78P468L

8-Bit Microcontroller

6Function Description

6.1Operational Registers

6.1.1R0/IAR (Indirect Addressing Register)

(Address: 00h)

R0 is not a physically implemented register. Its major function is to perform as an indirect address pointer. Any instruction using R0 as a register, actually accesses the data pointed by the RAM Select Register (R4).

6.1.2R1/TCC (Timer Clock Counter)

(Address: 01h)

The Timer Clock Counter is incremented by an external signal edge applied to TCC, or by the instruction cycle clock. It is written and read by the program as any other register.

6.1.3R2/PC (Program Counter)

(Address: 02h)

„The structure of R2 is depicted in Fig. 6-1, Program Counter Organization.

„The configuration structure generates 4K⋅13 bits on-chip ROM addresses to the relative programming instruction codes.

„The contents of R2 are all set to "0"s when a Reset condition occurs.

„"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows the PC to jump to any location within a page.

„"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed onto the stack. Thus, the subroutine entry address can be located anywhere within a page.

„"RET" ("RETL k", "RETI") instruction loads the program counter with the contents at the top of the stack.

„"ADD R2, A" allows a relative address to be added to the current PC, and the ninth and above bits of the PC will increase progressively.

„"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged.

„The most significant bits (A10~A11) will be loaded with the content of PS0~PS1 in the Status register (R3) upon execution of a "JMP" or "CALL" instruction.

6 •

Product Specification (V1.5) 02.15.2007

(This specification is subject to change without further notice)

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Contents EM78P468N/L Elan Microelectronics Corporation Contents Infrared Remote Control Application/PWM Waveform Generate Appendix Doc. Version Revision Description DateContents Product Specification V1.5 Features General DescriptionBit Microcontroller Pin Assignment Pin QFP Pin LqfpBlock Diagram System Block DiagramSymbol Pin No Type Function Pin DescriptionPin Description for Package of QFP64 and LQFP64 Pin Description for Package of QFP44 and LQFP44 SEG11~SEG142 R1/TCC Timer Clock Counter Function DescriptionOperational Registers 1 R0/IAR Indirect Addressing RegisterOn-ChipProgrammemory 4 R3/SR Status Register Bits 6 ~ 5 PS1 ~ 0 Page select bitsBit 2 Z Zero flag Bit 0 C Carry flag5 R4/RSR RAM Select Register 6 R5/Port 5 Port 5 I/O Data and Page of Register Select7 R6/Port 6 Port 6 I/O Data Register 8 R7/Port 7 Port 7 I/O Data RegisterBit 4 Lcden LCD enable bit 9 R8/Port 8 Port 8 I/O Data Register10 R9/LCDCR LCD Control Register Lcdtype = 0 a type waveform Lcdtype = 1 B type waveformRC/CNTER Counter Enable Register 11 RA/LCDADDR LCD AddressRB/LCDDB LCD Data Buffer 14 RD/SBPCR System, Booster and PLL Control Register Address 0DhMain clock Example Fs=32.768K15 RE/IRCR IR and Port 5 Setting Control Register Bit Microcontroller CPU Operation ModeAddress 0Eh 16 RF/ISR Interrupt Status Register Address 10h~3Fh R10~R3F General Purpose RegisterAddress 0Fh Special Purpose Registers AccumulatorAddress 05h, Bit 0 of R5 = 3 IOC60/P6CR Port 6 I/O Control Register 4 IOC70/P7CR Port 7 I/O Control Register5 IOC80/P8CR Port 8 I/O Control Register 6 IOC90/RAMADDR 128 Bytes RAM AddressIOCB0/CNT1PR Counter 1 Preset Register IOCC0/CNT2PR Counter 2 Preset RegisterIOCD0/HPWTPR High-Pulse Width Timer Preset Register IOCE0/LPWTPR Low-Pulse Width Timer Preset Register IOCF0/IMR Interrupt Mask RegisterBits 6, 5, 4 Not used 14 IOC71/TCCCR TCC Control Register Bit 7 IntedgeBits 3~0 PSRE, TCCP2 ~ TCCP0 TCC prescaler bits TCC Rate15 IOC81/WDTCR WDT Control Register 16 IOC91/CNT12CR Counters 1, 2 Control RegisterBits 7 ~ 4 Not used WDT RateIOCA1/HLPWTCR High/Low Pulse Width Timer Control Register Low-pulse Width Timer ScaleHigh-pulse Width Timer Scale Counter 1 ScaleIOCB1/P6PH Port 6 Pull-high Control Register IOCC1/P6OD Port 6 Open Drain Control RegisterIOCD1/P8PH Port 8 Pull High Control Register IOCE1/P6PL Port 6 Pull Low Control RegisterTCC and WDT Prescaler MUXBit Microcontroller WDT Setting Flowchart TCC Setting FlowchartReset and Wake-up I/O PortsAddress Name Reset Type Bit Bit Microcontroller Summary of Registers Initialized ValuesINT Psre TCCP2 TCCP1 TCCP0 Name Reset Type Bit Wake-up Signal Sleep Mode Idle Mode Green Mode Normal Mode Phase Lock Loop PLL Mode OscillatorOscillator Modes Crystal Oscillator/Ceramic Resonators Crystal Main clock Example Fs=32.768KHzOscillator Source Oscillator Type Frequency C1 pF C2 pF Power-on Considerations RC Oscillator Mode with Internal CapacitorRC Oscillator Frequencies Pin Rext Average Fosc 5V, 25 C Average Fosc 3V, 25 CExternal Power-on Reset Circuit Residue-Voltage ProtectionInterrupt 13 Interrupt Back-upLCD Driver 1 R9/LCDCR LCD Control RegisterBits 6 ~ 5 DS1 ~ DS0 LCD duty select 2 RA/LCDADDR LCD Address 3 RB/LCDDB LCD Data BufferBits 7 ~ 5 Not used, fixed to Bits 4 ~ 0 LCDA4 ~ LCDA0 LCD RAM address4 RD/SBPCR System, Booster and PLL Control Registers Bit 2 ~ 1 BF1 ~ 0 LCD booster frequency select bitsBoosting circuits connection for LCD voltage External circuit for 1/3 BiasExternal circuit for 1/2 Bias 16 LCD Waveform for 1/2 Bias, 1/2 Duty 18 LCD Waveform for 1/3 Bias, 1/3 Duty Infrared Remote Control Application/PWM Waveform Generate ⋅ 1 + decimal C ounter Preset Value Iocc 0 ⋅ prescaler21 LGP=0, Irout Pin Output Waveform 23 LGP=0, Irout Pin Output Waveform Bit Microcontroller IR/PWM Function Enable Flowchart IR applicationCode Options Bits 12 ~ 10 Not usedWord Bits12~10 WordInstruction Set Bits 2~0 PR2~PR0 Protect BitPR1PR0Protect Binary Instruction Hex Mnemonic Operation Status ConventionBinary Instruction Hex Mnemonic Operation Status Affected JZATiming Diagram AC Test Input/Output WaveformItems Symbol Condition Rating Min Max Unit Absolute Maximum RatingsElectrical Characteristic DC Electrical CharacteristicsSymbol Parameter Condition Min Typ Max Unit Ta= -40 C ~85 C, VDD= 5.0V, GND=Ta= -40C ~85 C, VDD= 3.0V, GND= AC Electrical Characteristics Symbol Parameter Conditions Min Typ Max UnitTa=- 40C ~ 85 C, VDD=5V±5%, GND=0V Device Characteristic Vih/Vil /RESET pins with schmitt inverterVih/Vil Port 7, Port 8 All Input pins with schmitt inverter P5.7 Voh/Ioh VDD=5V, IROCS=1 P5.7 Voh/Ioh VDD=3V, IROCS=1 80 P5.7 Voh/Ioh VDD=5V, IROCS=0 Max Typ +25 Setup time from Power on Reset = 51 K 13 Typical Eric OSC Frequency vs. Temperature Xin Pin VDD=5V Typical ICC2 vs. Temerature Typical ICC1 vs. Temerature Typical ISB vs. Temerature 22 Operating Voltage under Temperature Range of 0C to 70C Application Circuit Package Type Name Package Type Pin Count Package SizeEM78P468NxS/xJ Package Information QFPLqfp 900 100 BSC 00 REFMin Normal Max 30TYP 15TYP Wiring diagram is for Elan Dwtr EM78P468N/L Program Pin ListProgram Pin Name IC Pin Name QFP-64 QFP-44 Main oscillator Crystal mode, Sub oscillator Crystal mode Main oscillator PLL mode, Sub oscillator Crystal modeICE 468XA Oscillator Circuit JP Main oscillator RC mode, Sub oscillator CrystalBit Microcontroller ICE 468XA Output Pin Assignment JP VLCD3 GND OscoQuality Assurance and Reliability Address Trap DetectTest Category Test Conditions Contents III

MiEM78P468L, MiEM78P468N specifications

The IBM MiEM78P468N and MiEM78P468L are advanced integrated circuit solutions that cater primarily to the needs of enterprise-level computing systems. These microprocessors are integral in handling a variety of complex tasks, thereby empowering businesses with the efficiency and speed required in today's fast-paced digital environment.

Both models utilize the cutting-edge 78P architecture, which provides impressive performance capabilities. The MiEM78P468N operates at a clock speed of up to 2.2 GHz, while the MiEM78P468L offers a lower clock speed optimized for energy efficiency. This distinction makes the N version ideal for high-performance applications, whereas the L version appeals to scenarios where power consumption is a critical consideration.

A key characteristic of both models is their multi-core architecture, supporting up to four cores. This feature allows for enhanced parallel processing, enabling the handling of multiple tasks simultaneously—a vital requirement for data-intensive applications. Moreover, the inclusion of advanced cache memory arrangements enhances data retrieval speeds significantly, ensuring that applications run smoothly without performance bottlenecks.

These processors also employ cutting-edge thermal management technologies. The dynamic voltage and frequency scaling (DVFS) capabilities ensure that performance can be adjusted in real-time based on workload requirements, helping to minimize energy consumption. This is particularly beneficial in maintaining optimal operating temperatures and prolonging the lifespan of the hardware.

Another notable feature is support for advanced security protocols. Both models incorporate hardware-based security technologies that safeguard data integrity and protect against unauthorized access. This is becoming increasingly important in today's cybersecurity landscape where businesses must prioritize protecting sensitive information.

Additionally, the IBM MiEM78P468N and MiEM78P468L processors are compatible with a wide range of operating systems, facilitating seamless integration into various IT environments. Their robust architecture supports extensive peripheral interconnect protocols, enhancing expandability and connectivity options.

In summary, the IBM MiEM78P468N and MiEM78P468L processors stand out for their performance capabilities, energy efficiency, advanced security features, and versatility. They are well-suited for organizations looking to enhance their computing power while maintaining a balance between performance and power consumption. These microprocessors are instrumental in driving innovation and efficiency in enterprise computing.
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