IBM MiEM78P468N, MiEM78P468L manual 15 RE/IRCR IR and Port 5 Setting Control Register, Address 0Eh

Page 19

EM78P468N/EM78P468L

8-Bit Microcontroller

CPU Operation Mode

 

 

 

Code option

 

 

 

 

HLFS=1

RESET

 

 

 

 

 

 

 

 

 

 

 

Normal Mode

 

Code option

 

 

fm:oscillation

 

 

 

 

HLFS=0

 

 

fs:oscillation

 

 

it must delay a little times for the main

 

CPU: using fosc

 

 

oscillation stable w hile your system timing

 

 

 

 

control is conscientious

 

 

 

 

 

 

 

 

 

CPUS="0"

CPUS="1"

SLEEP Mode

 

IDLE="0"

Green Mode

 

SLEP

 

 

 

Fm:stop

 

 

 

fm:stop

Fs: stop

 

 

 

fs:oscillation

CPU: stop

 

Wake up

CPU: usingfs

 

 

 

 

 

The w ake up time from sleep to green mode is approximately sub-oscillator setup time +18ms+16*1/fs

 

IDLE="1"

IDLE Mode

 

SLEP

 

 

 

 

 

fm:stop

 

 

 

fs:oscillation

 

w akeup

CPU: stop

 

 

 

 

The w ake up time from idle to green mode is 16*1/fs

Fig. 6-3 CPU Operation Mode

6.1.15 RE/IRCR (IR and Port 5 Setting Control Register)

(Address: 0Eh)

Bit 7

Bit 6

 

Bit 5

Bit

4

Bit 3

Bit 2

 

Bit 1

Bit 0

 

 

IRE

HF

LGP

 

IROUTE

TCCE

EINT1

EINT0

Bit 7 (IRE): Infrared Remote Enable bit

IRE = “0” : Disable the IR/PWM function. The state of P5.7/IROUT pin is determined by Bit 7 of IOC 50 if it is for IROUT.

IRE = “1” : Enable IR or PWM function.

Bit 6 (HF): High carry frequency

HF = “0” : For PWM application, disable the H/W modulator function. The IROUT waveform is generated according to high-pulse and low-pulse time as determined by the respective high pulse and low pulse width timers. Counter 2 is an independent auto reload timer.

HF = “1” : For IR application mode, enable the H/W modulator function, the low time sections of the generated pulse is modulated with the Fcarrier frequency. The Fcarrier frequency is provided by Counter 2.

Bit 5 (LGP): IROUT for of low pulse width timer

LGP = “0” : The high-pulse width timer register and low-pulse width timer is valid.

LGP = “1” : The high-pulse width timer register is ignored. So the IROUT waveform is dependent on the low-pulse width timer register only.

Product Specification (V1.5) 02.15.2007

13

(This specification is subject to change without further notice)

Image 19
Contents EM78P468N/L Elan Microelectronics Corporation Contents Infrared Remote Control Application/PWM Waveform Generate Doc. Version Revision Description Date AppendixContents Product Specification V1.5 General Description FeaturesBit Microcontroller Pin QFP Pin Lqfp Pin AssignmentSystem Block Diagram Block DiagramPin Description Symbol Pin No Type FunctionPin Description for Package of QFP64 and LQFP64 SEG11~SEG14 Pin Description for Package of QFP44 and LQFP441 R0/IAR Indirect Addressing Register 2 R1/TCC Timer Clock CounterFunction Description Operational RegistersOn-ChipProgrammemory Bit 0 C Carry flag 4 R3/SR Status RegisterBits 6 ~ 5 PS1 ~ 0 Page select bits Bit 2 Z Zero flag8 R7/Port 7 Port 7 I/O Data Register 5 R4/RSR RAM Select Register6 R5/Port 5 Port 5 I/O Data and Page of Register Select 7 R6/Port 6 Port 6 I/O Data RegisterLcdtype = 0 a type waveform Lcdtype = 1 B type waveform Bit 4 Lcden LCD enable bit9 R8/Port 8 Port 8 I/O Data Register 10 R9/LCDCR LCD Control Register11 RA/LCDADDR LCD Address RC/CNTER Counter Enable RegisterRB/LCDDB LCD Data Buffer Example Fs=32.768K 14 RD/SBPCR System, Booster and PLL Control RegisterAddress 0Dh Main clockBit Microcontroller CPU Operation Mode 15 RE/IRCR IR and Port 5 Setting Control RegisterAddress 0Eh Address 10h~3Fh R10~R3F General Purpose Register 16 RF/ISR Interrupt Status RegisterAddress 0Fh Accumulator Special Purpose RegistersAddress 05h, Bit 0 of R5 = 6 IOC90/RAMADDR 128 Bytes RAM Address 3 IOC60/P6CR Port 6 I/O Control Register4 IOC70/P7CR Port 7 I/O Control Register 5 IOC80/P8CR Port 8 I/O Control RegisterIOCC0/CNT2PR Counter 2 Preset Register IOCB0/CNT1PR Counter 1 Preset RegisterIOCD0/HPWTPR High-Pulse Width Timer Preset Register IOCF0/IMR Interrupt Mask Register IOCE0/LPWTPR Low-Pulse Width Timer Preset RegisterBits 6, 5, 4 Not used TCC Rate 14 IOC71/TCCCR TCC Control RegisterBit 7 Intedge Bits 3~0 PSRE, TCCP2 ~ TCCP0 TCC prescaler bitsWDT Rate 15 IOC81/WDTCR WDT Control Register16 IOC91/CNT12CR Counters 1, 2 Control Register Bits 7 ~ 4 Not usedCounter 1 Scale IOCA1/HLPWTCR High/Low Pulse Width Timer Control RegisterLow-pulse Width Timer Scale High-pulse Width Timer ScaleIOCE1/P6PL Port 6 Pull Low Control Register IOCB1/P6PH Port 6 Pull-high Control RegisterIOCC1/P6OD Port 6 Open Drain Control Register IOCD1/P8PH Port 8 Pull High Control RegisterMUX TCC and WDT PrescalerTCC Setting Flowchart Bit Microcontroller WDT Setting FlowchartI/O Ports Reset and Wake-upBit Microcontroller Summary of Registers Initialized Values Address Name Reset Type BitINT Psre TCCP2 TCCP1 TCCP0 Name Reset Type Bit Wake-up Signal Sleep Mode Idle Mode Green Mode Normal Mode Oscillator Phase Lock Loop PLL ModeOscillator Modes Main clock Example Fs=32.768KHz Crystal Oscillator/Ceramic Resonators CrystalOscillator Source Oscillator Type Frequency C1 pF C2 pF Pin Rext Average Fosc 5V, 25 C Average Fosc 3V, 25 C Power-on ConsiderationsRC Oscillator Mode with Internal Capacitor RC Oscillator FrequenciesResidue-Voltage Protection External Power-on Reset Circuit13 Interrupt Back-up Interrupt1 R9/LCDCR LCD Control Register LCD DriverBits 6 ~ 5 DS1 ~ DS0 LCD duty select Bits 4 ~ 0 LCDA4 ~ LCDA0 LCD RAM address 2 RA/LCDADDR LCD Address3 RB/LCDDB LCD Data Buffer Bits 7 ~ 5 Not used, fixed toBit 2 ~ 1 BF1 ~ 0 LCD booster frequency select bits 4 RD/SBPCR System, Booster and PLL Control RegistersExternal circuit for 1/3 Bias Boosting circuits connection for LCD voltageExternal circuit for 1/2 Bias 16 LCD Waveform for 1/2 Bias, 1/2 Duty 18 LCD Waveform for 1/3 Bias, 1/3 Duty ⋅ 1 + decimal C ounter Preset Value Iocc 0 ⋅ prescaler Infrared Remote Control Application/PWM Waveform Generate21 LGP=0, Irout Pin Output Waveform 23 LGP=0, Irout Pin Output Waveform IR application Bit Microcontroller IR/PWM Function Enable FlowchartBits12~10 Word Code OptionsBits 12 ~ 10 Not used WordBits 2~0 PR2~PR0 Protect Bit Instruction SetPR1PR0Protect Convention Binary Instruction Hex Mnemonic Operation StatusJZA Binary Instruction Hex Mnemonic Operation Status AffectedAC Test Input/Output Waveform Timing DiagramAbsolute Maximum Ratings Items Symbol Condition Rating Min Max UnitTa= -40 C ~85 C, VDD= 5.0V, GND= Electrical CharacteristicDC Electrical Characteristics Symbol Parameter Condition Min Typ Max UnitTa= -40C ~85 C, VDD= 3.0V, GND= Symbol Parameter Conditions Min Typ Max Unit AC Electrical CharacteristicsTa=- 40C ~ 85 C, VDD=5V±5%, GND=0V Vih/Vil /RESET pins with schmitt inverter Device CharacteristicVih/Vil Port 7, Port 8 All Input pins with schmitt inverter P5.7 Voh/Ioh VDD=5V, IROCS=1 P5.7 Voh/Ioh VDD=3V, IROCS=1 80 P5.7 Voh/Ioh VDD=5V, IROCS=0 Max Typ +25 Setup time from Power on Reset = 51 K 13 Typical Eric OSC Frequency vs. Temperature Xin Pin VDD=5V Typical ICC2 vs. Temerature Typical ICC1 vs. Temerature Typical ISB vs. Temerature 22 Operating Voltage under Temperature Range of 0C to 70C Application Circuit Name Package Type Pin Count Package Size Package TypeEM78P468NxS/xJ QFP Package Information900 100 BSC 00 REF LqfpMin Normal Max 30TYP 15TYP EM78P468N/L Program Pin List Wiring diagram is for Elan DwtrProgram Pin Name IC Pin Name QFP-64 QFP-44 Main oscillator RC mode, Sub oscillator Crystal Main oscillator Crystal mode, Sub oscillator Crystal modeMain oscillator PLL mode, Sub oscillator Crystal mode ICE 468XA Oscillator Circuit JPBit Microcontroller VLCD3 GND Osco ICE 468XA Output Pin Assignment JPAddress Trap Detect Quality Assurance and ReliabilityTest Category Test Conditions Contents III

MiEM78P468L, MiEM78P468N specifications

The IBM MiEM78P468N and MiEM78P468L are advanced integrated circuit solutions that cater primarily to the needs of enterprise-level computing systems. These microprocessors are integral in handling a variety of complex tasks, thereby empowering businesses with the efficiency and speed required in today's fast-paced digital environment.

Both models utilize the cutting-edge 78P architecture, which provides impressive performance capabilities. The MiEM78P468N operates at a clock speed of up to 2.2 GHz, while the MiEM78P468L offers a lower clock speed optimized for energy efficiency. This distinction makes the N version ideal for high-performance applications, whereas the L version appeals to scenarios where power consumption is a critical consideration.

A key characteristic of both models is their multi-core architecture, supporting up to four cores. This feature allows for enhanced parallel processing, enabling the handling of multiple tasks simultaneously—a vital requirement for data-intensive applications. Moreover, the inclusion of advanced cache memory arrangements enhances data retrieval speeds significantly, ensuring that applications run smoothly without performance bottlenecks.

These processors also employ cutting-edge thermal management technologies. The dynamic voltage and frequency scaling (DVFS) capabilities ensure that performance can be adjusted in real-time based on workload requirements, helping to minimize energy consumption. This is particularly beneficial in maintaining optimal operating temperatures and prolonging the lifespan of the hardware.

Another notable feature is support for advanced security protocols. Both models incorporate hardware-based security technologies that safeguard data integrity and protect against unauthorized access. This is becoming increasingly important in today's cybersecurity landscape where businesses must prioritize protecting sensitive information.

Additionally, the IBM MiEM78P468N and MiEM78P468L processors are compatible with a wide range of operating systems, facilitating seamless integration into various IT environments. Their robust architecture supports extensive peripheral interconnect protocols, enhancing expandability and connectivity options.

In summary, the IBM MiEM78P468N and MiEM78P468L processors stand out for their performance capabilities, energy efficiency, advanced security features, and versatility. They are well-suited for organizations looking to enhance their computing power while maintaining a balance between performance and power consumption. These microprocessors are instrumental in driving innovation and efficiency in enterprise computing.