IBM MiEM78P468N, MiEM78P468L Special Purpose Registers, Accumulator, Address 05h, Bit 0 of R5 =

Page 21

EM78P468N/EM78P468L

8-Bit Microcontroller

6.2 Special Purpose Registers

6.2.1A (Accumulator)

Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register.

„Registers of IOC Page 0 (IOC50 ~ IOCF0, Bit 0 of R5 = “0”)

6.2.2IOC50/P5CR (Port 5 I/O and Ports 7, 8 for LCD Segment Control Register)

(Address: 05h, Bit 0 of R5 = “0”)

Bit 7

Bit 6

 

Bit 5

Bit 4

Bit 3

Bit 2

 

Bit 1

Bit 0

 

 

IOC57

IOC56

IOC55

IOC54

P8HS

P8LS

P7HS

P7LS

 

 

 

 

 

 

 

 

 

 

Bits 7~4 (IOC57~54): Port 5 I/O direction control register

IOC5x = “0”: set the relative P5.x I/O pins as output

IOC5x = “1”: set the relative P5.x I/O pin into high impedance (input pin)

Bit 3 (P8HS): Switch to high nibble I/O of Port 8 or to LCD segment output while sharing

pins with SEGxx/P8.x pins.

P8HS = “0”: select high nibble of Port 8 as normal P8.4~P8.7

P8HS = “1”: select LCD segment output as SEG 28~SEG 31 output

Bit 2 (P8LS): Switch to low nibble I/O of Port 8 or to LCD segment output while sharing pins with SEGxx/P8.x pins

P8LS = ”0”: select low nibble of Port 8 as normal P8.0~P8.3

P8LS = ”1”: select LCD Segment output as SEG 24~SEG 27 output

Bit 1 (P7HS): Switch to high nibble I/O of Port 7 or to LCD segment output while sharing

pins with SEGxx/P7.x pins

P7HS = “0”: select high nibble of Port 7 as normal P7.4~P7.7

P7HS = “1”: select LCD Segment output as SEG 20~SEG 23 output

Bit 0 (P7LS): Switch to low nibble I/O of Port 7 or to LCD segment output while sharing pins with SEGxx/P7.x pins

P7LS = “0”: select low nibble of Port 7 as normal P7.0~P7.3

P7LS = “1”: select LCD segment output as SEG 16~SEG 19 output

Product Specification (V1.5) 02.15.2007

• 15

(This specification is subject to change without further notice)

Page 20 Page 22
Image 21
Page 20 Page 22
Contents EM78P468N/L Elan Microelectronics Corporation Contents Infrared Remote Control Application/PWM Waveform Generate Doc. Version Revision Description Date AppendixContents Product Specification V1.5 Features General DescriptionBit Microcontroller Pin QFP Pin Lqfp Pin AssignmentSystem Block Diagram Block DiagramSymbol Pin No Type Function Pin DescriptionPin Description for Package of QFP64 and LQFP64 SEG11~SEG14 Pin Description for Package of QFP44 and LQFP44Function Description 2 R1/TCC Timer Clock CounterOperational Registers 1 R0/IAR Indirect Addressing RegisterOn-ChipProgrammemory Bits 6 ~ 5 PS1 ~ 0 Page select bits 4 R3/SR Status RegisterBit 2 Z Zero flag Bit 0 C Carry flag6 R5/Port 5 Port 5 I/O Data and Page of Register Select 5 R4/RSR RAM Select Register7 R6/Port 6 Port 6 I/O Data Register 8 R7/Port 7 Port 7 I/O Data Register9 R8/Port 8 Port 8 I/O Data Register Bit 4 Lcden LCD enable bit10 R9/LCDCR LCD Control Register Lcdtype = 0 a type waveform Lcdtype = 1 B type waveformRC/CNTER Counter Enable Register 11 RA/LCDADDR LCD AddressRB/LCDDB LCD Data Buffer Address 0Dh 14 RD/SBPCR System, Booster and PLL Control RegisterMain clock Example Fs=32.768K15 RE/IRCR IR and Port 5 Setting Control Register Bit Microcontroller CPU Operation ModeAddress 0Eh 16 RF/ISR Interrupt Status Register Address 10h~3Fh R10~R3F General Purpose RegisterAddress 0Fh Special Purpose Registers AccumulatorAddress 05h, Bit 0 of R5 = 4 IOC70/P7CR Port 7 I/O Control Register 3 IOC60/P6CR Port 6 I/O Control Register5 IOC80/P8CR Port 8 I/O Control Register 6 IOC90/RAMADDR 128 Bytes RAM AddressIOCB0/CNT1PR Counter 1 Preset Register IOCC0/CNT2PR Counter 2 Preset RegisterIOCD0/HPWTPR High-Pulse Width Timer Preset Register IOCE0/LPWTPR Low-Pulse Width Timer Preset Register IOCF0/IMR Interrupt Mask RegisterBits 6, 5, 4 Not used Bit 7 Intedge 14 IOC71/TCCCR TCC Control RegisterBits 3~0 PSRE, TCCP2 ~ TCCP0 TCC prescaler bits TCC Rate16 IOC91/CNT12CR Counters 1, 2 Control Register 15 IOC81/WDTCR WDT Control RegisterBits 7 ~ 4 Not used WDT RateLow-pulse Width Timer Scale IOCA1/HLPWTCR High/Low Pulse Width Timer Control RegisterHigh-pulse Width Timer Scale Counter 1 ScaleIOCC1/P6OD Port 6 Open Drain Control Register IOCB1/P6PH Port 6 Pull-high Control RegisterIOCD1/P8PH Port 8 Pull High Control Register IOCE1/P6PL Port 6 Pull Low Control RegisterMUX TCC and WDT PrescalerTCC Setting Flowchart Bit Microcontroller WDT Setting FlowchartI/O Ports Reset and Wake-upBit Microcontroller Summary of Registers Initialized Values Address Name Reset Type BitINT Psre TCCP2 TCCP1 TCCP0 Name Reset Type Bit Wake-up Signal Sleep Mode Idle Mode Green Mode Normal Mode Phase Lock Loop PLL Mode OscillatorOscillator Modes Crystal Oscillator/Ceramic Resonators Crystal Main clock Example Fs=32.768KHzOscillator Source Oscillator Type Frequency C1 pF C2 pF RC Oscillator Mode with Internal Capacitor Power-on ConsiderationsRC Oscillator Frequencies Pin Rext Average Fosc 5V, 25 C Average Fosc 3V, 25 CResidue-Voltage Protection External Power-on Reset Circuit13 Interrupt Back-up InterruptLCD Driver 1 R9/LCDCR LCD Control RegisterBits 6 ~ 5 DS1 ~ DS0 LCD duty select 3 RB/LCDDB LCD Data Buffer 2 RA/LCDADDR LCD AddressBits 7 ~ 5 Not used, fixed to Bits 4 ~ 0 LCDA4 ~ LCDA0 LCD RAM addressBit 2 ~ 1 BF1 ~ 0 LCD booster frequency select bits 4 RD/SBPCR System, Booster and PLL Control RegistersBoosting circuits connection for LCD voltage External circuit for 1/3 BiasExternal circuit for 1/2 Bias 16 LCD Waveform for 1/2 Bias, 1/2 Duty 18 LCD Waveform for 1/3 Bias, 1/3 Duty ⋅ 1 + decimal C ounter Preset Value Iocc 0 ⋅ prescaler Infrared Remote Control Application/PWM Waveform Generate21 LGP=0, Irout Pin Output Waveform 23 LGP=0, Irout Pin Output Waveform IR application Bit Microcontroller IR/PWM Function Enable FlowchartBits 12 ~ 10 Not used Code OptionsWord Bits12~10 WordInstruction Set Bits 2~0 PR2~PR0 Protect BitPR1PR0Protect Convention Binary Instruction Hex Mnemonic Operation StatusJZA Binary Instruction Hex Mnemonic Operation Status AffectedAC Test Input/Output Waveform Timing DiagramAbsolute Maximum Ratings Items Symbol Condition Rating Min Max UnitDC Electrical Characteristics Electrical CharacteristicSymbol Parameter Condition Min Typ Max Unit Ta= -40 C ~85 C, VDD= 5.0V, GND=Ta= -40C ~85 C, VDD= 3.0V, GND= AC Electrical Characteristics Symbol Parameter Conditions Min Typ Max UnitTa=- 40C ~ 85 C, VDD=5V±5%, GND=0V Vih/Vil /RESET pins with schmitt inverter Device CharacteristicVih/Vil Port 7, Port 8 All Input pins with schmitt inverter P5.7 Voh/Ioh VDD=5V, IROCS=1 P5.7 Voh/Ioh VDD=3V, IROCS=1 80 P5.7 Voh/Ioh VDD=5V, IROCS=0 Max Typ +25 Setup time from Power on Reset = 51 K 13 Typical Eric OSC Frequency vs. Temperature Xin Pin VDD=5V Typical ICC2 vs. Temerature Typical ICC1 vs. Temerature Typical ISB vs. Temerature 22 Operating Voltage under Temperature Range of 0C to 70C Application Circuit Package Type Name Package Type Pin Count Package SizeEM78P468NxS/xJ QFP Package Information900 100 BSC 00 REF LqfpMin Normal Max 30TYP 15TYP Wiring diagram is for Elan Dwtr EM78P468N/L Program Pin ListProgram Pin Name IC Pin Name QFP-64 QFP-44 Main oscillator PLL mode, Sub oscillator Crystal mode Main oscillator Crystal mode, Sub oscillator Crystal modeICE 468XA Oscillator Circuit JP Main oscillator RC mode, Sub oscillator CrystalBit Microcontroller VLCD3 GND Osco ICE 468XA Output Pin Assignment JPQuality Assurance and Reliability Address Trap DetectTest Category Test Conditions Contents III

MiEM78P468L, MiEM78P468N specifications

The IBM MiEM78P468N and MiEM78P468L are advanced integrated circuit solutions that cater primarily to the needs of enterprise-level computing systems. These microprocessors are integral in handling a variety of complex tasks, thereby empowering businesses with the efficiency and speed required in today's fast-paced digital environment.

Both models utilize the cutting-edge 78P architecture, which provides impressive performance capabilities. The MiEM78P468N operates at a clock speed of up to 2.2 GHz, while the MiEM78P468L offers a lower clock speed optimized for energy efficiency. This distinction makes the N version ideal for high-performance applications, whereas the L version appeals to scenarios where power consumption is a critical consideration.

A key characteristic of both models is their multi-core architecture, supporting up to four cores. This feature allows for enhanced parallel processing, enabling the handling of multiple tasks simultaneously—a vital requirement for data-intensive applications. Moreover, the inclusion of advanced cache memory arrangements enhances data retrieval speeds significantly, ensuring that applications run smoothly without performance bottlenecks.

These processors also employ cutting-edge thermal management technologies. The dynamic voltage and frequency scaling (DVFS) capabilities ensure that performance can be adjusted in real-time based on workload requirements, helping to minimize energy consumption. This is particularly beneficial in maintaining optimal operating temperatures and prolonging the lifespan of the hardware.

Another notable feature is support for advanced security protocols. Both models incorporate hardware-based security technologies that safeguard data integrity and protect against unauthorized access. This is becoming increasingly important in today's cybersecurity landscape where businesses must prioritize protecting sensitive information.

Additionally, the IBM MiEM78P468N and MiEM78P468L processors are compatible with a wide range of operating systems, facilitating seamless integration into various IT environments. Their robust architecture supports extensive peripheral interconnect protocols, enhancing expandability and connectivity options.

In summary, the IBM MiEM78P468N and MiEM78P468L processors stand out for their performance capabilities, energy efficiency, advanced security features, and versatility. They are well-suited for organizations looking to enhance their computing power while maintaining a balance between performance and power consumption. These microprocessors are instrumental in driving innovation and efficiency in enterprise computing.
Top Page Image Contents