IBM EM78P809N manual CPU Operation Mode, Registers for CPU operation mode, Rbank, Name

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EM78P809N

8-Bit Microcontroller

Bit 3 ( TBIE ) : Time base timer interrupt enable bit.

TBIE = “0” : disable TBIF interrupt

TBIE = “1” : enable TBIF interrupt

Bit 2 ( EXIE1 ) : External INT 1 Interrupt enable bit.

EXIE1 = “0” : disable EXIF1 interrupt

EXIE1 = “1” : enable EXIF1 interrupt

Bit 0 ( TCIE0 ) : TCC Interrupt enable bit.

TCIE0 = “0” : disable TCIF0 interrupt

TCIE0 = “1” : enable TCIF0 interrupt

Individual interrupt is enabled by setting its associated control bit in the IMR2 to "1".

Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.

IMR2 register is both readable and writable.

4.4CPU Operation Mode

Registers for CPU operation mode

R_BANK

Address

NAME

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BANK 0

0X05

SCR

0

PS2

PS1

PS0

0

1

SIS

REM

--

R/W

R/W

R/W

--

--

R/W

R/W

* R_BANK: Register Bank (bits 7, 6 of R3), R/W: Read/Write

Reset Occurs

IDLE MODE

CPU : Halts

Fosc: Oscillates

SIS=0 + SLEP							SIS=1 + SLEP

				NORMAL MODE						SLEEP MODE
				NORMAL MODE						SLEEP MODE
				CPU : Operating						CPU : Halts
				Fosc: Oscillates						Fosc: Stops
				Fosc: Oscillates						Fosc: Stops

Interrupt							/SLEEP Pin Input

Fig 5. Operation Mode and Switching

Product Specification (V1.0) 07.26.2005

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(This specification is subject to change without further notice)

Image 31

Contents DOC. Version EM78P809NElan Microelectronics Corporation Contents Specification Revision History Bit Microcontroller CPU„ General purpose ApplicationsPin Assignment OTP Programming Pins Function Description Functional Block DiagramTbktc Operating RegistersR2/PC − Program Counter & Stack Address 02h R1/TCC − Time Clock /Counter Address 01hRBS1 RBS0 R3/SR − Status Register Address 03hBit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page select Bit 5 Not usedGRBS1 GRBS0 Bit 0 C Carry flag R4/RSR − RAM Select Register Address 04hGeneral Purpose Register Bank Address 20H ~ 3FH PORT8 − Port 8 I/O Data Register Address 08h SIS = 0 Idle mode SIS = 1 Sleep modePORT6 − Port 6 I/O Data Register Address 06h PORT7 Port 7 I/O Data Register Address 07hTC4CK2 TC4CK1 TC4CK0 TC4CR Timer/Counter 4 Control Register Address 0BhTC4S = 1 Start TC4FF1 TC4FF0ISFR1 − Interrupt Status Flag Register 1 Address 0Eh Bit Microcontroller TC4D − Timer 4 Data Buffer Address 0ChTC3CAP TC3S TC3CK1 TC3CK0 TC3M Bit 7 TC3CAP Software capture controlTC3CAP = TC3S = 1 StartTC2S = 1 Start TC3DB − Timer 3 Data Buffer B Address 07hTC2M = 1 Window mode Bit 7 ~ Bit 6 ADD1 ~ ADD0 AD low 2-bit data bufferTC2DL − Timer 2 Data Buffer Low Byte Address 0Ah TC2DH − Timer 2 Data Buffer High Byte Address 09hAdcr − AD Control Register Address 0Bh Addh − AD High 8-bit Data Buffer Address 0Dh Bit 3 ADP AD power controlBit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable control Adic − AD Input Pin Control Address 0ChBit Microcontroller Tbktc − TBT/Keytone Control Address 0Eh Bit 7 TEN Keytone enable controlTEN = 0 Disable TEN = 1 Enable Bit 3 Tbten Time Base Timer Enable ControlBit 4 ~ Bit 2 BRATE2 ~ BRATE1 Transmit Baud Rate Select Bit 3 Uinven Enable Uart TXD and RXD port inverse outputUinven = 0 Disable TXD and RXD port inverse output Uinven = 1 Enable TXD and RXD port inverse outputBit Microcontroller URS − Uart Status Register Address 07h Bit 5 PRE Enable parity additionEven = 0 Odd parity Even = 1 Even parity EDS Dord WBE Bit 2 EDS Data shift out edge selectEDS = 0 Rising edge EDS = 1 Falling edge SMP Dcol BRS2 BRS1SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0 Transfer ModeSPIC2 − SPI Control Register 2 Address 06h Spid SPI Data Buffer Address 07hPLC2 − Pull Low Control 2 Address 0Dh PLE7x = 1 Disable P7x pull lowPLC1 Pull Low Control Register 1 Address 0Bh PHC2 − Pull High Control Register 2 Address 0ChBit 7 Wdto WDT output select Special Purpose RegistersAccumulator Control Register INT1ES = 0 Rising edge INT1ES = 1 Falling edge Bit Microcontroller IOC6 ~ IOC9 − I/O Port Control Register Intcr − INT Control Register Address 0Bh Bit 2 ReservedEdge INT Pin Secondary Enable Condition Function PinExternal Interrupt Adoscr − AD Offset Control Register Address 0ChUerrie Urie Utie Tbie EXIE1 TCIE0 IMR2 − Interrupt Mask Register 2 Address 0FhRbank CPU Operation ModeRegisters for CPU operation mode Rbank Register Bank bits 7, 6 of R3, R/W Read/WriteOperation Mode Mode Switching ControlNormal → Don’t care → Interrupt request flag will be recorded AD ConverterRegisters for AD Converter Circuit Sampling Time ADC Data RegisterConversion Time ADCK10 Time Base Timer and Keytone GeneratorMax. Frequency Max. Conversion Rate per Bit Tone Output Pin Timing Chart Registers for Uart Circuit Uart Universal Asynchronous Receiver/TransmitterRbank Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Data Format in Uart Uart ModeReceiving TransmittingBaud Rate Generator SPI Serial Peripheral InterfaceRegisters for the SPI Circuit Serial Clock Shift Direction and Sample PhaseTransfer Mode Bit Transmit ModeBit Transmit/Receive Mode Bit Microcontroller Bit Receive ModeMultiple Device Connect /SS SCK pinRegisters for Timer/Counter 2 Circuit Timer/CounterRbank Address Name Bit 7 Bit 6 Bit Counter Mode Timer ModeWindow Mode Registers for Timer/Counter 3 Circuit Window Mode Timing ChartConfiguration of Timer/Counter3 Capture modeTCIF4 Registers for Timer 4 CircuitTCR4 PDO Mode12 TCC/WDT & Prescaler PWM ModeTC4 Interrupt Reset Reset and Wake-up13 I/O Ports Wake-up from Idle mode Wake-up from Sleep ModeAll interrupt Summary of the Initialized Values for Registers Address Name Reset Type BitSCR Bit Microcontroller Register BankTC2D9 TC2D8 Register Bank Bit Microcontroller General Purpose Registers Previous value before resetReset Type Status of RST, T, and P of Status RegisterInterrupt Controller Reset Block DiagramSummary of Maximum Operating Speeds OscillatorOscillator Modes Crystal Oscillator/Ceramic Resonators Crystal740 Oscillator Type Frequency Mode C1 pF C2 pFEM78P809N Ext. ClockCrystal/Resonator-Parallel Mode Circuit External RC Oscillator ModeFor design reference only Enwdtb = 0 Enable Enwdtb = 1 DisableCode Option Register Code Option Register WordCyes = 0 One cycle Cyes = 1 Two cycles Power-on ConsiderationsExternal Power-on Reset Circuit Customer ID RegisterVdd EM78P809N Residue-Voltage ProtectionVdd EM78P809N RinVdd 40KR2 Instruction SetDEC Binary Instruction Hex Mnemonic Operation Status AffectedVss = Symbol Parameter Condition Min Typ Max UnitAbsolute Maximum Ratings Recommended Operating ConditionsTa= 25 C, VDD= 5.0V ± 5%, VSS= DC Electrical CharacteristicsTypical value is based on characterization results at 25C Ta= 25 C, VDD= 3.0V ± 5%, VSS= Varef = selected prescaler ratio AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit Ta=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0VAC Test Input/Output Waveform Timing DiagramOTP MCU Package TypesPin Count Package Size Contents III EM78P809N