IBM EM78P809N manual Uart Mode, Data Format in Uart

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EM78P809N

8-Bit Microcontroller

In Universal Asynchronous Receiver Transmitter (UART), each transmitted or received character is individually synchronized by framing it with a start bit and stop bit.

Full duplex data transfer is possible since the UART has independent transmit and receive sections. Double buffering for both sections allows the UART to be programmed for continuous data transfer.

The figure below shows the general format of one character sent or received. The communication channel is normally held in the marked state (high). Character transmission or reception starts with a transition to the space state (low).

The first bit transmitted or received is the start bit (low). It is followed by the data bits, in which the least significant bit (LSB) comes first. The data bits are followed by the parity bit. If present, then the stop bit or bits (high) confirm the end of the frame.

In receiving, the UART synchronizes on the falling edge of the start bit. When two or three “0” are detected during three samples, it is recognized as normal start bit and the receiving operation is started.

							Idle state
START	D0	D1	D2	Dn	Parity	STOP	(mark)
bit	D0	D1	D2	Dn	bit	bit
bit					bit	bit
1 bit			7 or 8 bits		1 bit	1 bits
			One character or frame

Fig. 12. DATA Format in UART

4.7.1 UART MODE:

There are three UART modes. Mode 1 (7 bits data) and Mode 2 (8 bits data) allow the addition of a parity bit. The parity bit addition is not available in Mode 3. The Figure below shows the data format in each mode.

	UMODE		PRE	1	2	3	4	5	6	7	8	9	10	11
Mode 1	0	0	0	START			7 bits DATA					STOP
Mode 1
	0	0	1	START			7 bits DATA					Parity	STOP
Mode 2	0	1	0	START			8 bits DATA						STOP
Mode 2
	0	1	1	START			8 bits DATA						Parity	STOP
Mode 3	1	0	X	START			9 bits DATA							STOP

Fig. 13. UART Mode

34 •	Product Specification (V1.0) 07.26.2005

(This specification is subject to change without further notice)

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Contents EM78P809N DOC. VersionElan Microelectronics Corporation Contents Specification Revision History CPU Bit MicrocontrollerApplications „ General purposePin Assignment OTP Programming Pins Functional Block Diagram Function DescriptionOperating Registers TbktcR1/TCC − Time Clock /Counter Address 01h R2/PC − Program Counter & Stack Address 02hBit 5 Not used R3/SR − Status Register Address 03hBit 7 ~ Bit 6 RBS1 ~ RBS0 R-Register page select RBS1 RBS0General Purpose Register Bank Address 20H ~ 3FH Bit 0 C Carry flag R4/RSR − RAM Select Register Address 04hGRBS1 GRBS0 PORT7 Port 7 I/O Data Register Address 07h SIS = 0 Idle mode SIS = 1 Sleep modePORT6 − Port 6 I/O Data Register Address 06h PORT8 − Port 8 I/O Data Register Address 08hTC4FF1 TC4FF0 TC4CR Timer/Counter 4 Control Register Address 0BhTC4S = 1 Start TC4CK2 TC4CK1 TC4CK0Bit Microcontroller TC4D − Timer 4 Data Buffer Address 0Ch ISFR1 − Interrupt Status Flag Register 1 Address 0EhTC3S = 1 Start Bit 7 TC3CAP Software capture controlTC3CAP = TC3CAP TC3S TC3CK1 TC3CK0 TC3MBit 7 ~ Bit 6 ADD1 ~ ADD0 AD low 2-bit data buffer TC3DB − Timer 3 Data Buffer B Address 07hTC2M = 1 Window mode TC2S = 1 StartAdcr − AD Control Register Address 0Bh TC2DH − Timer 2 Data Buffer High Byte Address 09hTC2DL − Timer 2 Data Buffer Low Byte Address 0Ah Adic − AD Input Pin Control Address 0Ch Bit 3 ADP AD power controlBit 7 ~ Bit 0 ADE7 ~ ADE0 AD input pin enable control Addh − AD High 8-bit Data Buffer Address 0DhBit 3 Tbten Time Base Timer Enable Control Bit 7 TEN Keytone enable controlTEN = 0 Disable TEN = 1 Enable Bit Microcontroller Tbktc − TBT/Keytone Control Address 0EhUinven = 1 Enable TXD and RXD port inverse output Bit 3 Uinven Enable Uart TXD and RXD port inverse outputUinven = 0 Disable TXD and RXD port inverse output Bit 4 ~ Bit 2 BRATE2 ~ BRATE1 Transmit Baud Rate SelectEven = 0 Odd parity Even = 1 Even parity Bit 5 PRE Enable parity additionBit Microcontroller URS − Uart Status Register Address 07h SMP Dcol BRS2 BRS1 Bit 2 EDS Data shift out edge selectEDS = 0 Rising edge EDS = 1 Falling edge EDS Dord WBESpid SPI Data Buffer Address 07h Transfer ModeSPIC2 − SPI Control Register 2 Address 06h SPID7 SPID6 SPID5 SPID4 SPID3 SPID2 SPID1 SPID0PHC2 − Pull High Control Register 2 Address 0Ch PLE7x = 1 Disable P7x pull lowPLC1 Pull Low Control Register 1 Address 0Bh PLC2 − Pull Low Control 2 Address 0DhControl Register Special Purpose RegistersAccumulator Bit 7 Wdto WDT output selectBit 2 Reserved Bit Microcontroller IOC6 ~ IOC9 − I/O Port Control RegisterIntcr − INT Control Register Address 0Bh INT1ES = 0 Rising edge INT1ES = 1 Falling edgeAdoscr − AD Offset Control Register Address 0Ch INT Pin Secondary Enable Condition Function PinExternal Interrupt EdgeIMR2 − Interrupt Mask Register 2 Address 0Fh Uerrie Urie Utie Tbie EXIE1 TCIE0Rbank Register Bank bits 7, 6 of R3, R/W Read/Write CPU Operation ModeRegisters for CPU operation mode RbankNormal Mode Switching ControlOperation Mode Registers for AD Converter Circuit AD Converter→ Don’t care → Interrupt request flag will be recorded Conversion Time ADC Data RegisterSampling Time Max. Frequency Max. Conversion Rate per Bit Time Base Timer and Keytone GeneratorADCK10 Tone Output Pin Timing Chart Rbank Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Uart Universal Asynchronous Receiver/TransmitterRegisters for Uart Circuit Uart Mode Data Format in UartTransmitting ReceivingRegisters for the SPI Circuit SPI Serial Peripheral InterfaceBaud Rate Generator Bit Transmit Mode Shift Direction and Sample PhaseTransfer Mode Serial ClockBit Microcontroller Bit Receive Mode Bit Transmit/Receive ModeSCK pin Multiple Device Connect /SSRbank Address Name Bit 7 Bit 6 Bit Timer/CounterRegisters for Timer/Counter 2 Circuit Window Mode Timer ModeCounter Mode Window Mode Timing Chart Registers for Timer/Counter 3 CircuitCapture mode Configuration of Timer/Counter3Registers for Timer 4 Circuit TCIF4PDO Mode TCR4TC4 Interrupt PWM Mode12 TCC/WDT & Prescaler 13 I/O Ports Reset and Wake-upReset All interrupt Wake-up from Sleep ModeWake-up from Idle mode Address Name Reset Type Bit Summary of the Initialized Values for RegistersBit Microcontroller Register Bank SCRTC2D9 TC2D8 Register Bank Status of RST, T, and P of Status Register Previous value before resetReset Type Bit Microcontroller General Purpose RegistersController Reset Block Diagram InterruptCrystal Oscillator/Ceramic Resonators Crystal OscillatorOscillator Modes Summary of Maximum Operating SpeedsExt. Clock Oscillator Type Frequency Mode C1 pF C2 pFEM78P809N 740External RC Oscillator Mode Crystal/Resonator-Parallel Mode CircuitCode Option Register Word Enwdtb = 0 Enable Enwdtb = 1 DisableCode Option Register For design reference onlyCustomer ID Register Power-on ConsiderationsExternal Power-on Reset Circuit Cyes = 0 One cycle Cyes = 1 Two cyclesEM78P809N Rin Residue-Voltage ProtectionVdd Vdd EM78P809NInstruction Set Vdd 40KR2Binary Instruction Hex Mnemonic Operation Status Affected DECRecommended Operating Conditions Symbol Parameter Condition Min Typ Max UnitAbsolute Maximum Ratings Vss =Typical value is based on characterization results at 25C DC Electrical CharacteristicsTa= 25 C, VDD= 5.0V ± 5%, VSS= Ta= 25 C, VDD= 3.0V ± 5%, VSS= Varef Ta=- 40C ~ 85 C, VDD=5V ± 5%, VSS=0V AC Electrical CharacteristicSymbol Parameter Conditions Min Typ Max Unit = selected prescaler ratioTiming Diagram AC Test Input/Output WaveformPin Count Package Size Package TypesOTP MCU Contents III EM78P809N