Texas Instruments TMS320C645x manual Gpio Function

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GPIO Function

2 GPIO Function

You can independently configure each GPIO pin (GPn) as either an input or an output using the GPIO direction registers. The GPIO direction register (DIR) specifies the direction of each GPIO signal. Logic 0 indicates the GPIO pin is configured as output, and logic 1 indicates input.

When configured as output, writing a 1 to a bit in the set data register drives the corresponding GPn to a logic-high state. Writing a 1 to a bit in the clear data register drives the corresponding GPn to a logic-low state. The output state of each GPn can also be directly controlled by writing to the output data register. For example, to set GP8 to a logic-high state, the software can perform one of the following:

-Write 0x100 to the SET_DATA register

-Read in OUT_DATA register, change the eighth bit to 1, and write the new value back to OUT_DATA

To set GP8 to a logic-low state, the software can perform one of the following:

-Write 0x100 to the CLR_DATA register

-Read in OUT_DATA register, change the eighth bit to 0, and write the new value back to OUT_DATA

Note that writing a 0 to bits in the set data and clear data registers does not affect the GPIO pin state. Also, for GPIO pins configured as input, writing to the set data, clear data, or output data registers does not affect the pin state.

For a GPIO pin configured as input, reading the input data register (IN_DATA) will return the pin state.

Reading the SET_DATA register or the CLR_DATA data register will return the value in OUT_DATA, not the actual pin state. The pin state is available by reading the input data register.

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General-Purpose Input/Output (GPIO)

SPRU724

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Contents Literature Number SPRU724 December Important Notice Read This First About This ManualTrademarks Contents Figures Tables This page is intentionally left blank General-Purpose OverviewTMS320C645x DSP Block Diagram Gpio Peripheral Block Diagram Gpio Function Gpio Interrupt and Edma Event Configuration Options Interrupt and Event GenerationEmulation Halt Operation Registers Gpio RegistersInterrupt Per-Bank Enable Register Binten Interrupt Per-Bank Enable Register BintenDirection Register DIR Direction Register DIRDirection Register DIR Field Descriptions Output Data Register Outdata Output Data Register Outdata Field DescriptionsSet Data Register Setdata Set Data Register Setdata Field DescriptionsClear Data Register Clrdata Clear Data Register ClrdataClear Data Register Clrdata Field Descriptions Input Data Register Indata Input Data Register Indata Field DescriptionsSet Rising Edge Interrupt Register Setristrig Set Rising Edge Interrupt Register SetristrigClear Rising Edge Interrupt Register Clrristrig Clear Rising Edge Interrupt Register ClrristrigSet Falling Edge Interrupt Register Setfaltrig Set Falling Edge Interrupt Register SetfaltrigClear Falling Edge Interrupt Register Clrfaltrig Clear Falling Edge Interrupt Register ClrfaltrigThis page is intentionally left blank Index
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