Registers
5.9Set Falling Edge Interrupt Register (SET_FAL_TRIG)
The GPIO falling trigger register (FAL_TRIG) configures the edge detection logic to trigger GPIO interrupts and EDMA events on the falling edge of GPIO signals. Setting a bit to 1 in FAL_TRIG causes the corresponding GPIO interrupt and EDMA event (GPINTn) to be generated on the falling edge of GPn. FAL_TRIG is not directly accessible by the CPU; it must be configured using the GPIO set falling trigger and clear falling trigger registers.
The GPIO set falling trigger register (SET_FAL_TRIG) is shown in Figure 11 and described in Table 11. Writing a 1 to a bit of SET_FAL_TRIG sets the corresponding bit in FAL_TRIG. Writing a 0 has no effect. Reading SET_FAL_TRIG returns the value in FAL_TRIG.
Figure 11. Set Falling Edge Interrupt Register (SET_FAL_TRIG)
31 |
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| 16 |
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| Reserved |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
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SETFAL15 | SETFAL14 | SETFAL13 | SETFAL12 | SETFAL11 | SETFAL10 | SETFAL9 | SETFAL8 |
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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SETFAL7 | SETFAL6 | SETFAL5 | SETFAL4 | SETFAL3 | SETFAL2 | SETFAL1 | SETFAL0 |
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Legend: R = Read only; R/W = Read/Write;
Table 11. Set Falling Edge Interrupt Register (SET_FAL_TRIG) Field Descriptions
Bit | Field | Value | Description |
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31−16 | Reserved | 0 | Reserved. The reserved bit location is always read as zero. A value |
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| written to this field has no effect. |
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15−0 | SETFALn |
| Writing a 1 enables the falling edge detection for the corresponding GPn |
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| pin. Reading this register returns the state of the FAL_TRIG register. |
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| 0 | No effect |
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| 1 | Sets the corresponding bit in FAL_TRIG |
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24 | SPRU724 |