Texas Instruments TMS320C645x manual Clear Rising Edge Interrupt Register Clrristrig

Registers

5.8Clear Rising Edge Interrupt Register (CLR_RIS_TRIG)

The GPIO rising trigger register (RIS_TRIG) configures the edge detection logic to trigger GPIO interrupts and EDMA events on the rising edge of GPIO signals. Setting a bit to 1 in RIS_TRIG causes the corresponding GPIO interrupt and EDMA event (GPINTn) to be generated on the rising edge of GPn. RIS_TRIG is not directly accessible by the CPU; it must be configured using the GPIO set rising trigger and clear rising trigger registers.

The GPIO clear rising trigger register (CLR_RIS_TRIG) is shown in Figure 10 and described in Table 10. Writing a 1 to a bit of CLR_RIS_TRIG clears the corresponding bit in RIS_TRIG. Writing a 0 has no effect. Reading CLR_RIS_TRIG returns the value in RIS_TRIG.

Figure 10. Clear Rising Edge Interrupt Register (CLR_RIS_TRIG)

31							16
			Reserved
			R-0
15	14	13	12	11	10	9	8
CLRRIS15	CLRRIS14	CLRRIS13	CLRRIS12	CLRRIS11	CLRRIS10	CLRRIS9	CLRRIS8
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0
7	6	5	4	3	2	1	0
CLRRIS7	CLRRIS6	CLRRIS5	CLRRIS4	CLRRIS3	CLRRIS2	CLRRIS1	CLRRIS0
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

Legend: R = Read only; R/W = Read/Write; -n= value after reset

Table 10. Clear Rising Edge Interrupt Register (CLR_RIS_TRIG) Field Descriptions

Bit	Field	Value	Description
31−16	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to
			this field has no effect.
15−0	CLRRISn		Writing a 1 disables rising edge detection for the corresponding GPn pin.
			Reading this register returns the state of the RIS_TRIG register.
		0	No effect
		1	Clears the corresponding bit in RIS_TRIG

SPRU724 General-Purpose Input/Output (GPIO) 23