Texas Instruments TMS320C645x manual Interrupt Per-Bank Enable Register Binten

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Registers

5.1Interrupt Per-Bank Enable Register (BINTEN)

To use the GPIO pins as sources for CPU interrupts and EDMA events, bit 0 in the bank interrupt enable register (BINTEN) must be set. BINTEN is shown in Figure 3 and described in Table 3.

Figure 3.	Interrupt Per-Bank Enable Register (BINTEN)
31		1	0

	Reserved		EN

	R-0		RW-0
Legend: R = Read only; R/W = Read/Write; -n= value after reset

Table 3.	Interrupt Per-Bank Enable Register (BINTEN) Field Descriptions

Bit	Field	Value	Description

31−1	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to
			this field has no effect.

0	EN		Enables all GPIO pins as interrupt sources to the DSP CPU.
		0	Disables GPIO interrupts
		1	Enables GPIO interrupts

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General-Purpose Input/Output (GPIO)

SPRU724

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Contents Literature Number SPRU724 December Important Notice Read This First About This ManualTrademarks Contents Figures Tables This page is intentionally left blank General-Purpose OverviewTMS320C645x DSP Block Diagram Gpio Peripheral Block Diagram Gpio Function Gpio Interrupt and Edma Event Configuration Options Interrupt and Event GenerationEmulation Halt Operation Registers Gpio RegistersInterrupt Per-Bank Enable Register Binten Interrupt Per-Bank Enable Register BintenDirection Register DIR Direction Register DIRDirection Register DIR Field Descriptions Output Data Register Outdata Output Data Register Outdata Field DescriptionsSet Data Register Setdata Set Data Register Setdata Field DescriptionsClear Data Register Clrdata Clear Data Register ClrdataClear Data Register Clrdata Field Descriptions Input Data Register Indata Input Data Register Indata Field DescriptionsSet Rising Edge Interrupt Register Setristrig Set Rising Edge Interrupt Register SetristrigClear Rising Edge Interrupt Register Clrristrig Clear Rising Edge Interrupt Register ClrristrigSet Falling Edge Interrupt Register Setfaltrig Set Falling Edge Interrupt Register SetfaltrigClear Falling Edge Interrupt Register Clrfaltrig Clear Falling Edge Interrupt Register ClrfaltrigThis page is intentionally left blank Index

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