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  | Registers  | |
5  | Registers | 
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  | The GPIO peripheral is configured through the registers listed in Table 2. See  | |||
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  | the   | |||
Table 2.  | GPIO Registers | 
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Offsets | Acronym | Register Name | Section | ||
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0008  | 
  | BINTEN  | Interrupt   | 5.1  | 
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0010  | 
  | DIR  | Direction Register  | 5.2  | 
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0014  | 
  | OUT_DATA  | Output Data Register  | 5.3  | 
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0018  | 
  | SET_DATA  | Set Data Register  | 5.4  | 
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001C  | 
  | CLR_DATA  | Clear Data Register  | 5.5  | 
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0020  | 
  | IN_DATA  | Input Data Register  | 5.6  | 
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0024  | 
  | SET_RIS_TRIG  | Set Rising Edge Interrupt Register  | 5.7  | 
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0028  | 
  | CLR_RIS_TRIG  | Clear Rising Edge Interrupt Register  | 5.8  | 
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002C  | 
  | SET_FAL_TRIG  | Set Falling Edge Interrupt Register  | 5.8  | 
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0030  | 
  | CLR_FAL_TRIG  | Clear Falling Edge Interrupt Register  | 5.9  | 
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SPRU724 | 15  |