Texas Instruments
ADS5411
manual
Layer 2, Ground Plane
Parts list
Schematic Diagram
Output Connector J9
EVM Operational Procedure
Layer 3, Power Plane #1
Page 12
www.ti.com
PCB Layout
Figure
4-2.
Layer 2, Ground Plane
12
Physical Description
SLWU020B
–February
2005
–Revised
February 2006
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Image 12
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Page 13
Contents
Users Guide
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Contents
List of Figures
Power Requirements
EVM Operational Procedure
Overview
Purpose
Jumper Function Location Pins Default
Three Pin Jumper List Table
Schematic Diagram
Circuit Description
Circuit Function
Output Connector J9
Test Point Description
J9 PIN Description
Test Point Function
Parts List
Bill of Materials for EVM
Resistors
Value QTY Part Number Vendor REF DES Not Installed
ICs
Physical Description
PCB Layout
Layer 2, Ground Plane
Layer 3, Power Plane #1
Layer 4, Power Plane #2
Layer 5, Ground Plane
Layer 6, Bottom Layer
Schematics
Ti a
DRY
Drvdd
ADS5424
Evaluation BOARD/KIT Important Notice
FCC Warning
EVM Warnings and Restrictions
Important Notice
Related pages
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