Texas Instruments ADS5411 manual Layer 6, Bottom Layer

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PCB Layout

Figure 4-6. Layer 6, Bottom Layer

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Physical Description

SLWU020B –February 2005 –Revised February 2006

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Power Requirements EVM Operational ProcedureOverview PurposeJumper Function Location Pins Default Three Pin Jumper List TableCircuit Description Schematic DiagramCircuit Function Output Connector J9 Test Point DescriptionJ9 PIN Description Test Point FunctionBill of Materials for EVM Parts ListResistors Value QTY Part Number Vendor REF DES Not Installed ICsPhysical Description PCB LayoutLayer 2, Ground Plane Layer 3, Power Plane #1 Layer 4, Power Plane #2 Layer 5, Ground Plane Layer 6, Bottom Layer Schematics Ti a DRY Drvdd ADS5424 Evaluation BOARD/KIT Important Notice FCC Warning EVM Warnings and RestrictionsImportant Notice