Texas Instruments ADS5423 EVM, ADS5424 EVM, ADS5433 EVM, ADS5411 EVM manual Circuit Description

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Chapter 2

SLWU020B – February 2005 – Revised February 2006

Circuit Description

2.1Schematic Diagram

The schematic diagram for the EVM is attached at the end of this document.

2.2Circuit Function

The following paragraphs describe the function of EVM circuits. See the relevant data sheet for the device operating characteristics.

2.2.1 Analog Inputs

The EVM can be configured to provide the ADC with either transformer-coupled or differential amplifier inputs from a single-ended source. The default configuration uses the transformer configuration for which the layout has been optimized to give the best performance. The inputs are provided via SMA connectors J11 for transformer coupled input and J10 for differential amplifier input. To setup for one of these options, the EVM must be configured as follows:

1.For a 1:1 transformer coupled input to the ADC, a single ended source is connected to J11. SJP3 has pins 1 and 2 shorted and SJP4 has pins 2 and 3 shorted. This is the default configuration for the EVM.

2.For a differential input into the amplifier, the input source is connected to J10. SJP3 has pins 2 and 3 shorted and SJP4 has pins 1 and 2 shorted. ±5VDC must be connected to the board to provide power to U3 and U4 for this configuration.

2.2.2Power

Power is supplied to the EVM via banana jack sockets. A separate connection is provided for a +3.3V digital buffer supply (J1 and J2), 5-V analog supply (J3 and J2), ±5-V amplifier supply (J7, J8, and J12), and 3.3-V external buffer supply (J4 and J6). A single 3.3-V buffer supply could be used by installing L6. In this case, connect the 3.3 V to J1 and the return to J2.

2.2.3 Outputs

The data outputs from the ADC are buffered using a Texas Instruments SN74AVC16244. Output data header J9 is a standard 40-pin header on a 100-mil grid, and allows easy connection to a logic analyzer. The connector pinout is listed in Table 2-1. Furthermore, two test points are provided and can be monitored using a multimeter. Description of the test points is listed in Table 2-2.

SLWU020B –February 2005 –Revised February 2006

Circuit Description

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Purpose Power RequirementsEVM Operational Procedure OverviewThree Pin Jumper List Table Jumper Function Location Pins DefaultCircuit Description Schematic DiagramCircuit Function Test Point Function Output Connector J9Test Point Description J9 PIN DescriptionBill of Materials for EVM Parts ListResistors ICs Value QTY Part Number Vendor REF DES Not InstalledPCB Layout Physical DescriptionLayer 2, Ground Plane Layer 3, Power Plane #1 Layer 4, Power Plane #2 Layer 5, Ground Plane Layer 6, Bottom Layer Schematics Ti a DRY Drvdd ADS5424 Evaluation BOARD/KIT Important Notice EVM Warnings and Restrictions FCC WarningImportant Notice