Texas Instruments ADS5411 manual Layer 4, Power Plane #2

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PCB Layout

Figure 4-4. Layer 4, Power Plane #2

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Physical Description

SLWU020B –February 2005 –Revised February 2006

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Contents Users Guide Submit Documentation Feedback Contents List of Figures Overview Power RequirementsEVM Operational Procedure PurposeJumper Function Location Pins Default Three Pin Jumper List TableCircuit Function Schematic DiagramCircuit Description J9 PIN Description Output Connector J9Test Point Description Test Point FunctionResistors Parts ListBill of Materials for EVM Value QTY Part Number Vendor REF DES Not Installed ICsPhysical Description PCB LayoutLayer 2, Ground Plane Layer 3, Power Plane #1 Layer 4, Power Plane #2 Layer 5, Ground Plane Layer 6, Bottom Layer Schematics Ti a DRY Drvdd ADS5424 Evaluation BOARD/KIT Important Notice FCC Warning EVM Warnings and RestrictionsImportant Notice