Chapter 2: Installation
T-SGPIO 0/1 Headers
Two T-SGPIO (Serial-Link General Pur-
Pin Definitions
pose Input/Output) headers are located near the SATA connectors on the moth- erboard. These headers are used to communicate with the enclosure manage- ment chip in the system. See the table on
Pin#
1
3
5
7
Definition
NC
Ground
Load
Clock
Pin Definition
2 NC
4 DATA Out
6Ground
8NC
the right for pin definitions. Refer to the board layout below for the locations of the headers.
SATA DOM Power
The SATA DOM Power on JWF1 is used to supply power to SATA
NC: No Connections
A.T-SGPIO 1
B.
C.SATA DOM Power
| JPI2C |
|
| JPW1 |
|
KB/MOUSE | FLOPPY | FAN1 |
USB0/1 USB2/3 | JPUSB1 |
|
DIMM2B DIMM2A
COM1
VGA
LAN1/LAN2
JPL2 JPL1
DIMM1B DIMM1A DIMM2C
DDR3 1066/1333 UDIMM/RDIMM required | DIMM1C | FAN2/CPUFAN |
FAN2 |
LE1
JLED
JF1
CPU
IPMI_LAN
JF1
|
|
|
|
FAN5 |
| SLOT7 | |
|
|
|
|
|
|
|
|
JPB:BMC
Hermon
X8SIA
COM2
SLOT6 |
SLOT5
SLOT4
SLOT3
JPG1
JI2C1 | SLOT2 |
|
|
|
| JWOL: | |
JI2C2 | ||||
| Wake on Lan |
SLOT1 PCI 33MHz |
USB5
JWOR |
|
|
|
Wake on Ring | IPMB | USB6/7 | USB8/9 |
PCH |
+
USB4 | CMOS CLEAR |
JBT1 |
FAN3
+
JL1:
JD1
JWF1
B
A
C