5.0Gbps PCI Express Passive Switches
MAX4888A/MAX4889A
Test Circuits/Timing Diagrams (continued)
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| 3.3V |
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| V+ |
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RS | NO_+ OR | MAX4888A/MAX4889A |
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NC_+ |
| COM_+ |
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IN+ |
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| OUT+ | ||
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| RL | ||
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| tSK1 = D I F F E R E N C E I N P R O PA G AT I O N D E L AY ( R I S E - FA L L ) | ||
RS | NO_- OR |
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| BETWEEN ANY TWO PAIRS | |
| COM_- |
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NC_- |
| tSK2 = tPLHX - tPHLY OR tPHLX - tPLHY | |||
IN- |
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| OUT- | BETWEEN TWO LINES ON THE SAME PAIR | ||
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| RL |
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| SEL |
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| tINRISE |
| tINFALL |
1.5V |
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| 90% | 90% |
VIN+ |
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50% | 50% |
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0V |
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| 10% |
| 10% |
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1.5V |
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VIN- | 50% | 50% |
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0V |
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| tOUTRISE | tOUTFALL | |
tPLHX |
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| tPHLX |
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1.5V |
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| 90% | 90% |
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VOUT+ |
| 50% | 50% |
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0V |
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| 10% | 10% | |
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1.5V |
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VOUT- |
| 50% | 50% |
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0V |
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tPHLY |
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| tPLHY |
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Figure 2. Propagation Delay and Output Skew
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