Cypress CY7B992, CY7B991 manual Pin Configuration, Pin Definitions, Signal Name Description

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CY7B991

CY7B992

Pin Configuration

PLCC/LCC

3F0

FS

 

V

REF

 

GND

TEST

 

2F1

 

 

 

 

 

CCQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3F1

4F0

4F1

VCCQ

VCCN

4Q1

4Q0 GND GND

 

 

 

4

3

 

2

1

 

32

31

3029

2F0

 

5

 

 

 

6

 

 

 

 

 

 

 

 

 

 

 

 

28

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

 

 

 

 

 

27

1F1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

CY7B991

 

 

26

1F0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

 

 

 

 

 

25

VCCN

 

 

 

 

 

 

 

 

 

 

 

 

CY7B992

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

24

1Q0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

 

 

 

 

 

 

 

 

 

 

23

1Q1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

 

 

22

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

 

 

 

 

 

 

 

 

 

 

21

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

15

 

16

17

 

18

 

19

 

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3Q1

3Q0 V

FB V

2Q1

2Q0

 

CCN

CCN

 

 

Pin Definitions

Signal Name

IO

Description

REF

I

Reference frequency input. This input supplies the frequency and timing against which all functional

 

 

variations are measured.

 

 

 

FB

I

PLL feedback input (typically connected to one of the eight outputs).

 

 

 

FS

I

Three level frequency range select. See Table 1.

 

 

 

1F0, 1F1

I

Three level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.

 

 

 

2F0, 2F1

I

Three level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.

 

 

 

3F0, 3F1

I

Three level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.

 

 

 

4F0, 4F1

I

Three level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.

 

 

 

TEST

I

Three level select. See “Test Mode” on page 4 under the “Block Diagram Description” on page 3.

 

 

 

1Q0, 1Q1

O

Output pair 1. See Table 2.

 

 

 

2Q0, 2Q1

O

Output pair 2. See Table 2.

 

 

 

3Q0, 3Q1

O

Output pair 3. See Table 2.

 

 

 

4Q0, 4Q1

O

Output pair 4. See Table 2.

 

 

 

VCCN

PWR

Power supply for output drivers.

VCCQ

PWR

Power supply for internal circuitry.

GND

PWR

Ground.

 

 

 

Document Number: 38-07138 Rev. *B

Page 2 of 19

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Contents Functional Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion CourtPin Definitions Pin ConfigurationSignal Name Description Block Diagram Description Test Mode Typical Outputs with FB Connected to a Zero-Skew OutputAmbient Range Maximum RatingsOperating Range Electrical Characteristics Parameter Description Test Conditions CapacitanceAC Test Loads and Waveforms Input Capacitance = 25 C, f = 1 MHz, V CC =Switching Characteristics Over the Operating Range2 Parameter Description Min Typ Max UnitCY7B991-5 CY7B992-5 Parameter Description Unit Min Typ Max Propagation Delay, REF Rise to FB RiseOver the Operating Range2 Zero Output Skew All Outputs 16+0.7 Switching CharacteristicsCY7B991-7 CY7B992-7 Parameter Description Unit Min Typ Max +1.5AC Timing Diagrams Operational Mode Descriptions Programmable Skew Clock DriverInverted Output Connections Multi-Function Clock Driver Board-to-Board Clock Distribution Pb-Free Ordering InformationAccuracy Ordering Code Package Type Operating Range Package Diagrams Military SpecificationsDC Characteristics SubgroupsPin Rectangular Leadless Chip Carrier Issue Date Orig. Description of Change Document History

CY7B991, CY7B992 specifications

The Cypress CY7B992 and CY7B991 are advanced synchronous SRAM devices designed for high-speed applications, particularly in the field of telecommunications, networking, and high-performance computing. These SRAMs are notable for their ability to operate at high frequencies, making them suitable for systems that require rapid data access and processing.

One of the main features of the CY7B992 and CY7B991 is their support for synchronous operation, which allows for data transfers aligned with a clock signal. This capability significantly enhances performance by reducing access times and increasing data throughput compared to traditional asynchronous SRAMs. With their optimized write and read cycles, these devices can achieve low latency, enabling efficient data handling in real-time applications.

Another key technology utilized in these devices is the use of a 2-port architecture, which supports simultaneous read and write operations. This dual-port design allows for greater flexibility and efficiency in data management, making it easier to implement complex memory architectures in various applications. The architecture also supports burst mode operation, allowing for rapid sequential data access, which is crucial in environments where speed is paramount.

The CY7B992 and CY7B991 feature a wide data bus width, accommodating 32 bits to suit modern data processing needs. Their compact size and ease of integration into existing systems make them popular choices among designers and engineers. Moreover, these SRAMs offer a comprehensive range of voltage and temperature specifications, ensuring reliable performance across diverse operating conditions.

In terms of power management, the CY7B992 and CY7B991 are designed to consume low power while maintaining high performance, making them ideal for battery-operated or energy-sensitive applications. The devices include various power-saving features, such as power-down modes, enabling users to reduce overall system power consumption when the memory is not actively in use.

Overall, the Cypress CY7B992 and CY7B991 are robust, high-speed SRAM solutions that cater to the demands of sophisticated, data-intensive applications. Their synchronous operation, dual-port architecture, and efficient power management characteristics make them essential components in modern electronic systems. As technology continues to evolve, these SRAMs are poised to play a critical role in advancing the capabilities of next-generation devices.