Cypress CY7B991, CY7B992 manual Features, Functional Description, Logic Block Diagram

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CY7B991

CY7B992

Programmable Skew Clock Buffer

Features

■All output pair skew <100 ps typical (250 maximum)

■3.75 to 80 MHz output operation

■User selectable output functions

❐Selectable skew to 18 ns

❐Inverted and non-inverted

❐Operation at 1⁄2 and 1⁄4 input frequency

❐Operation at 2x and 4x input frequency (input as low as 3.75 MHz)

■Zero input to output delay

■50% duty cycle outputs

■Outputs drive 50Ω terminated lines

■Low operating current

■32-pin PLCC/LCC package

■Jitter < 200 ps peak-to-peak (< 25 ps RMS)

Functional Description

The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer user selectable control over system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to optimize the timing of high perfor- mance computer systems. Each of the eight individual drivers, arranged in four pairs of user controllable outputs, can drive terminated transmission lines with impedances as low as 50Ω. They can deliver minimal and specified output skews and full swing logic levels (CY7B991 TTL or CY7B992 CMOS).

Each output is hardwired to one of the nine delay or function configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs that skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows cancellation of external load and trans- mission line delay effects. When this “zero delay” capability of the PSCB is combined with the selectable output skew functions, you can create output-to-output delays of up to ±12 time units.

Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions enable distribution of a low frequency clock that are multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty, allowing maximum system clock speed and flexibility.

Logic Block Diagram

TEST

FB

 

PHASE

 

 

 

 

FREQ

 

FILTER

 

 

 

 

 

 

 

 

REF

 

 

DET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4F0

 

 

 

 

4F1

 

 

SELECT

 

 

 

 

INPUTS

 

(THREE

3F0

LEVEL)

 

 

 

 

3F1

 

 

 

 

 

 

 

2F0

2F1

1F0

1F1

VCO AND

TIME UNIT GENERATOR

SKEW

SELECT

MATRIX

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

Cypress Semiconductor Corporation • 198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document Number: 38-07138 Rev. *B

 

 

Revised June 22, 2007

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Contents Logic Block Diagram FeaturesFunctional Description Cypress Semiconductor Corporation 198 Champion CourtSignal Name Description Pin ConfigurationPin Definitions Block Diagram Description Typical Outputs with FB Connected to a Zero-Skew Output Test ModeOperating Range Maximum RatingsAmbient Range Electrical Characteristics AC Test Loads and Waveforms CapacitanceParameter Description Test Conditions Input Capacitance = 25 C, f = 1 MHz, V CC =Parameter Description Min Typ Max Unit Switching Characteristics Over the Operating Range2Over the Operating Range2 Propagation Delay, REF Rise to FB RiseCY7B991-5 CY7B992-5 Parameter Description Unit Min Typ Max Zero Output Skew All Outputs 16CY7B991-7 CY7B992-7 Parameter Description Unit Min Typ Max Switching Characteristics+0.7 +1.5AC Timing Diagrams Programmable Skew Clock Driver Operational Mode DescriptionsInverted Output Connections Multi-Function Clock Driver Board-to-Board Clock Distribution Accuracy Ordering Code Package Type Operating Range Ordering InformationPb-Free DC Characteristics Military SpecificationsPackage Diagrams SubgroupsPin Rectangular Leadless Chip Carrier Document History Issue Date Orig. Description of Change

CY7B991, CY7B992 specifications

The Cypress CY7B992 and CY7B991 are advanced synchronous SRAM devices designed for high-speed applications, particularly in the field of telecommunications, networking, and high-performance computing. These SRAMs are notable for their ability to operate at high frequencies, making them suitable for systems that require rapid data access and processing.

One of the main features of the CY7B992 and CY7B991 is their support for synchronous operation, which allows for data transfers aligned with a clock signal. This capability significantly enhances performance by reducing access times and increasing data throughput compared to traditional asynchronous SRAMs. With their optimized write and read cycles, these devices can achieve low latency, enabling efficient data handling in real-time applications.

Another key technology utilized in these devices is the use of a 2-port architecture, which supports simultaneous read and write operations. This dual-port design allows for greater flexibility and efficiency in data management, making it easier to implement complex memory architectures in various applications. The architecture also supports burst mode operation, allowing for rapid sequential data access, which is crucial in environments where speed is paramount.

The CY7B992 and CY7B991 feature a wide data bus width, accommodating 32 bits to suit modern data processing needs. Their compact size and ease of integration into existing systems make them popular choices among designers and engineers. Moreover, these SRAMs offer a comprehensive range of voltage and temperature specifications, ensuring reliable performance across diverse operating conditions.

In terms of power management, the CY7B992 and CY7B991 are designed to consume low power while maintaining high performance, making them ideal for battery-operated or energy-sensitive applications. The devices include various power-saving features, such as power-down modes, enabling users to reduce overall system power consumption when the memory is not actively in use.

Overall, the Cypress CY7B992 and CY7B991 are robust, high-speed SRAM solutions that cater to the demands of sophisticated, data-intensive applications. Their synchronous operation, dual-port architecture, and efficient power management characteristics make them essential components in modern electronic systems. As technology continues to evolve, these SRAMs are poised to play a critical role in advancing the capabilities of next-generation devices.
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