Cypress CY7B992, CY7B991 manual Test Mode, Typical Outputs with FB Connected to a Zero-Skew Output

Page 4

CY7B991

CY7B992

Figure 1 shows the typical outputs with FB connected to a zero skew output.[4]

Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output

 

 

U

U

U

U

U

U

 

U

U

U

U

U

U

 

 

– 6t

– 5t

– 4t

– 3t

– 2t

– 1t

 

+1t

+2t

+3t

+4t

+5t

+6t

 

 

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

t

t

t

t

t

t

t

t

t

t

t

t

t

 

 

FBInput

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REFInput

 

 

 

 

 

 

 

 

 

 

 

 

1Fx

3Fx

 

 

 

 

 

 

 

 

 

 

 

 

 

2Fx

4Fx

 

 

 

 

 

 

 

 

 

 

 

 

 

(N/A)

LM

– 6t U

 

 

 

 

 

 

 

 

 

 

 

 

LL

LH

– 4t U

 

 

 

 

 

 

 

 

 

 

 

 

LM

(N/A)

– 3t U

 

 

 

 

 

 

 

 

 

 

 

 

LH

ML

– 2t U

 

 

 

 

 

 

 

 

 

 

 

 

ML

(N/A)

– 1t U

 

 

 

 

 

 

 

 

 

 

 

 

MM

MM

0tU

 

 

 

 

 

 

 

 

 

 

 

 

MH

(N/A)

+1t U

 

 

 

 

 

 

 

 

 

 

 

 

HL

MH

+2t U

 

 

 

 

 

 

 

 

 

 

 

 

HM

(N/A)

+3t U

 

 

 

 

 

 

 

 

 

 

 

 

HH

HL

+4t U

 

 

 

 

 

 

 

 

 

 

 

 

(N/A)

HM

+6t U

 

 

 

 

 

 

 

 

 

 

 

 

(N/A)

LL/HH

DIVIDED

 

 

 

 

 

 

 

 

 

 

 

 

(N/A)

HH

INVERT

 

 

 

 

 

 

 

 

 

 

 

 

Test Mode

The TEST input is a three level input. In normal system operation, this pin is connected to ground, enabling the CY7B991 or CY7B992 to operate as explained in “Skew Select Matrix” on page 3. For testing purposes, any of the three level inputs can have a removable jumper to ground, or be tied LOW through a 100Ω resistor. This enables an external tester to change the state of these pins.

If the TEST input is forced to its MID or HIGH state, the device operates with its internal phase locked loop disconnected, and input levels supplied to REF directly controls all outputs. Relative output to output functions are the same as in normal mode.

In contrast with normal operation (TEST tied LOW), all outputs function based only on the connection of their own function selects inputs (xF0 and xF1) and the waveform characteristics of the REF input.

Note

4. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID).

Document Number: 38-07138 Rev. *B

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Contents Features Logic Block DiagramFunctional Description Cypress Semiconductor Corporation 198 Champion CourtSignal Name Description Pin ConfigurationPin Definitions Block Diagram Description Test Mode Typical Outputs with FB Connected to a Zero-Skew OutputOperating Range Maximum RatingsAmbient Range Electrical Characteristics Capacitance AC Test Loads and WaveformsParameter Description Test Conditions Input Capacitance = 25 C, f = 1 MHz, V CC =Switching Characteristics Over the Operating Range2 Parameter Description Min Typ Max UnitPropagation Delay, REF Rise to FB Rise Over the Operating Range2CY7B991-5 CY7B992-5 Parameter Description Unit Min Typ Max Zero Output Skew All Outputs 16Switching Characteristics CY7B991-7 CY7B992-7 Parameter Description Unit Min Typ Max+0.7 +1.5AC Timing Diagrams Operational Mode Descriptions Programmable Skew Clock DriverInverted Output Connections Multi-Function Clock Driver Board-to-Board Clock Distribution Accuracy Ordering Code Package Type Operating Range Ordering InformationPb-Free Military Specifications DC CharacteristicsPackage Diagrams SubgroupsPin Rectangular Leadless Chip Carrier Issue Date Orig. Description of Change Document History

CY7B991, CY7B992 specifications

The Cypress CY7B992 and CY7B991 are advanced synchronous SRAM devices designed for high-speed applications, particularly in the field of telecommunications, networking, and high-performance computing. These SRAMs are notable for their ability to operate at high frequencies, making them suitable for systems that require rapid data access and processing.

One of the main features of the CY7B992 and CY7B991 is their support for synchronous operation, which allows for data transfers aligned with a clock signal. This capability significantly enhances performance by reducing access times and increasing data throughput compared to traditional asynchronous SRAMs. With their optimized write and read cycles, these devices can achieve low latency, enabling efficient data handling in real-time applications.

Another key technology utilized in these devices is the use of a 2-port architecture, which supports simultaneous read and write operations. This dual-port design allows for greater flexibility and efficiency in data management, making it easier to implement complex memory architectures in various applications. The architecture also supports burst mode operation, allowing for rapid sequential data access, which is crucial in environments where speed is paramount.

The CY7B992 and CY7B991 feature a wide data bus width, accommodating 32 bits to suit modern data processing needs. Their compact size and ease of integration into existing systems make them popular choices among designers and engineers. Moreover, these SRAMs offer a comprehensive range of voltage and temperature specifications, ensuring reliable performance across diverse operating conditions.

In terms of power management, the CY7B992 and CY7B991 are designed to consume low power while maintaining high performance, making them ideal for battery-operated or energy-sensitive applications. The devices include various power-saving features, such as power-down modes, enabling users to reduce overall system power consumption when the memory is not actively in use.

Overall, the Cypress CY7B992 and CY7B991 are robust, high-speed SRAM solutions that cater to the demands of sophisticated, data-intensive applications. Their synchronous operation, dual-port architecture, and efficient power management characteristics make them essential components in modern electronic systems. As technology continues to evolve, these SRAMs are poised to play a critical role in advancing the capabilities of next-generation devices.
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