Cypress CY7C1329H manual Write Cycle Timing17

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CY7C1329H

Switching Waveforms (continued)

Write Cycle Timing[17, 18]

CLK

ADSP

ADSC

ADDRESS

BWE,

BW[A :D]

GW

CE

ADV

OE

Data In (D)

		tCYC
	tCH	tCL
tADS	tADH
		tADS	tADH	ADSC extends burst
		tADS	tADH	tADS	tADH
				tADS	tADH
tAS	tAH
	A1			A2	A3
	Byte write signals are
	ignored for first cycle when				tWES tWEH
	ADSP initiates burst				tWES tWEH

tWES tWEH

tCES	tCEH
								tADVS tADVH
				ADV suspends burst
	tDS tDH
High-Z	D(A1)	D(A2)	D(A2 + 1)	D(A2 + 1)	D(A2 + 2)	D(A2 + 3)	D(A3)	D(A3 + 1)	D(A3 + 2)
	t
	OEHZ

Data Out (Q)

BURST READ

Single WRITE

	BURST WRITE
DON’T CARE	UNDEFINED

Extended BURST WRITE

Note:

18. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A : D] LOW.

Document #: 38-05673 Rev. *B

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Contents Features Logic Block DiagramCypress Semiconductor Corporation Pin Configuration Selection GuideCY7C1329H 166 MHz 133 MHz UnitPin Definitions Functional Overview Burst SequencesInterleaved Burst Address Table Mode = Floating or VDD First Second Third Fourth Address A1, A0Truth Table for Read/Write 2 Next Cycle Add. UsedFunction CY7C1329H Electrical Characteristics Over the Operating Range8 Maximum RatingsOperating Range Ambient RangeCapacitance10 Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Over the Operating Range 11 Switching Waveforms Read Cycle Timing17Write Cycle Timing17 Read/Write Cycle Timing17, 19 CLZZZ Mode Timing21 DON’T CarePackage Diagram Ordering InformationPin Tqfp 14 x 20 x 1.4 mm Issue Date Orig. Description of Change Document History