Cypress CY7C1329H manual Maximum Ratings, Electrical Characteristics Over the Operating Range8

CY7C1329H

Maximum Ratings

(Above which the useful life may be impaired. For user guide- lines, not tested.)

Storage Temperature		–65°C to +150°C
Ambient Temperature with
Power Applied		–55°C to +125°C
Supply Voltage on VDD Relative to GND		–0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND		–0.5V to +VDD
DC Voltage Applied to Outputs
in Tri-State	–0.5V to VDDQ + 0.5V

Electrical Characteristics Over the Operating Range[8, 9]

DC Input Voltage	–0.5V to VDD + 0.5V
Current into Outputs (LOW)	20 mA
Static Discharge Voltage	> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current	> 200 mA

Operating Range

	Ambient
Range	Temperature	VDD	VDDQ
Commercial	0°C to +70°C	3.3V	2.5V –5%
		–5%/+10%	to VDD
Industrial	–40°C to +85°C

Parameter	Description	Test Conditions		Min.	Max.	Unit
VDD	Power Supply Voltage			3.135	3.6	V
VDDQ	I/O Supply Voltage	for 3.3V I/O		3.135	VDD	V
		for 2.5V I/O		2.375	2.625	V
VOH	Output HIGH Voltage	for 3.3V I/O, IOH = –4.0 mA		2.4	V	V
		for 2.5V I/O, IOH = –1.0 mA		2.0	V	V
VOL	Output LOW Voltage	for 3.3V I/O, IOL = 8.0 mA			0.4	V
		for 2.5V I/O, IOL = 1.0 mA			0.4	V
VIH	Input HIGH Voltage[8]	for 3.3V I/O		2.0	VDD + 0.3V	V
		for 2.5V I/O		1.7	VDD + 0.3V	V
VIL	Input LOW Voltage[8]	for 3.3V I/O		–0.3	0.8	V
		for 2.5V I/O		–0.3	0.7	V
IX	Input Leakage Current	GND ≤ VI ≤ VDDQ		–5	5	∝A
	except ZZ and MODE
	Input Current of MODE	Input = VSS		–30		∝A
		Input = VDD			5	∝A
	Input Current of ZZ	Input = VSS		–5		∝A
		Input = VDD			30	∝A
IOZ	Output Leakage Current	GND ≤ VI ≤ VDDQ, Output Disabled		–5	5	∝A
IDD	VDD Operating Supply	VDD = Max., IOUT = 0 mA,	6-ns cycle,166 MHz		240	mA
	Current	f = fMAX = 1/tCYC
			7.5-ns cycle,133 MHz		225	mA
ISB1	Automatic CS	VDD = Max, Device	6-ns cycle, 166 MHz		100	mA
	Power-down	Deselected, VIN ≥ VIH or
			7.5-ns cycle,133 MHz		90	mA
	Current—TTL Inputs	VIN ≤ VIL, f = fMAX = 1/tCYC
ISB2	Automatic CS	VDD = Max, Device	All speeds		40	mA
	Power-down	Deselected, VIN ≤ 0.3V or
	Current—CMOS Inputs	VIN > VDDQ – 0.3V, f = 0
ISB3	Automatic CS	VDD = Max, Device	6-ns cycle, 166 MHz		85	mA
	Power-down	Deselected, or VIN ≤ 0.3V
			7.5-ns cycle,133MHz		75	mA
	Current—CMOS Inputs	or VIN > VDDQ – 0.3V,
		f = fMAX = 1/tCYC
ISB4	Automatic CS	VDD = Max, Device	All speeds		45	mA
	Power-down	Deselected, VIN ≥ VIH or
	Current—TTL Inputs	VIN ≤ VIL, f = 0

Notes:

8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).

9. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 10. Tested initially and after any design or process change that may affect these parameters.

Document #: 38-05673 Rev. *B Page 8 of 16

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