Cypress CY7C1329H manual Switching Waveforms, Read Cycle Timing17

Page 11

CY7C1329H

Switching Waveforms

Read Cycle Timing[17]

tCYC

CLK

tCH

tADS tADH

ADSP

ADSC

tAS tAH

tCL

tADS tADH

ADDRESS

GW, BWE, BW[A:D]

A1

A2	A3
tWES tWEH	Burst continued with
tWES tWEH	new base address

CE

ADV

OE

Data Out (Q)

tCES tCEH

	tADVS	tADVH
				ADV
				suspends
				burst.
		tOEV	tCO
	tOEHZ	tOELZ	tDOH
	tCLZ
High-Z	Q(A1)		Q(A2)	Q(A2 + 1)	Q(A2 + 2)	Q(A2 + 3)
	tCO
	Single READ				BURST READ
			DON’T CARE	UNDEFINED

Deselect cycle

tCHZ

Q(A2)

Q(A2 + 1)

Burst wraps around to its initial state

Note:

17. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05673 Rev. *B

Page 11 of 16

[+] Feedback

Image 11

Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram 166 MHz 133 MHz Unit Pin ConfigurationSelection Guide CY7C1329HPin Definitions Burst Sequences Functional OverviewFirst Second Third Fourth Address A1, A0 Interleaved Burst Address Table Mode = Floating or VDDFunction Truth Table for Read/Write 2Next Cycle Add. Used CY7C1329H Ambient Range Electrical Characteristics Over the Operating Range8Maximum Ratings Operating RangeAC Test Loads and Waveforms Capacitance10Thermal Resistance Switching Characteristics Over the Operating Range 11 Read Cycle Timing17 Switching WaveformsWrite Cycle Timing17 CLZ Read/Write Cycle Timing17, 19DON’T Care ZZ Mode Timing21Pin Tqfp 14 x 20 x 1.4 mm Package DiagramOrdering Information Document History Issue Date Orig. Description of Change