Cypress CY7C1329H manual Document History, Issue Date Orig. Description of Change

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CY7C1329H

Document History Page

Document Title: CY7C1329H 2-Mbit (64K x 32) Pipelined Sync SRAM

Document Number: 38-05673

REV.	ECN NO.	Issue Date	Orig. of	Description of Change
REV.	ECN NO.	Issue Date	Change	Description of Change

**	347357	See ECN	PCI	New Data Sheet

*A	424820	See ECN	RXU	Converted from Preliminary to Final.
				Changed address of Cypress Semiconductor Corporation on Page# 1 from
				“3901 North First Street” to “198 Champion Court”
				Changed Three-State to Tri-State.
				Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
				Electrical Characteristics Table.
				Modified test condition from VIH < VDD to VIH < VDD
				Replaced Package Name column with Package Diagram in the Ordering
				Information table.
				Updated the Ordering Information Table.
				Replaced Package Diagram of 51-85050 from A to B
*B	433014	See ECN	NXR	Included 3.3V I/O option
				Updated the Ordering Information table.

Document #: 38-05673 Rev. *B

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Contents Logic Block Diagram FeaturesCypress Semiconductor Corporation Pin Configuration Selection GuideCY7C1329H 166 MHz 133 MHz UnitPin Definitions Functional Overview Burst SequencesInterleaved Burst Address Table Mode = Floating or VDD First Second Third Fourth Address A1, A0Next Cycle Add. Used Truth Table for Read/Write 2Function CY7C1329H Electrical Characteristics Over the Operating Range8 Maximum RatingsOperating Range Ambient RangeThermal Resistance Capacitance10AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 11 Switching Waveforms Read Cycle Timing17Write Cycle Timing17 Read/Write Cycle Timing17, 19 CLZZZ Mode Timing21 DON’T CareOrdering Information Package DiagramPin Tqfp 14 x 20 x 1.4 mm Issue Date Orig. Description of Change Document History