Cypress CY7C1329H manual Read/Write Cycle Timing17, 19, Clz

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Read/Write Cycle Timing[17, 19, 20]

A3 A4

tWES tWEH

tDS tDH

A5 A6

D(A3)

tOELZ

Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

D(A5) D(A6)

Back-to-Back READs

Single WRITE	BURST READ
DON’T CARE	UNDEFINED

Back-to-Back

WRITEs

Notes:

19.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

20.GW is HIGH.

Document #: 38-05673 Rev. *B

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Contents Logic Block Diagram FeaturesCypress Semiconductor Corporation Selection Guide Pin ConfigurationCY7C1329H 166 MHz 133 MHz UnitPin Definitions Burst Sequences Functional OverviewFirst Second Third Fourth Address A1, A0 Interleaved Burst Address Table Mode = Floating or VDDNext Cycle Add. Used Truth Table for Read/Write 2Function CY7C1329H Maximum Ratings Electrical Characteristics Over the Operating Range8Operating Range Ambient RangeThermal Resistance Capacitance10AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 11 Read Cycle Timing17 Switching WaveformsWrite Cycle Timing17 CLZ Read/Write Cycle Timing17, 19DON’T Care ZZ Mode Timing21Ordering Information Package DiagramPin Tqfp 14 x 20 x 1.4 mm Document History Issue Date Orig. Description of Change