Cypress CY7C1302DV25 manual Thermal Resistance20, Capacitance20, AC Test Loads and Waveforms

CY7C1302DV25

Thermal Resistance[20]

Parameter	Description	Test Conditions	165 FBGA Package	Unit
ΘJA	Thermal Resistance (Junction to Ambient)	Test conditions follow standard test	16.7	°C/W
		methods and procedures for measuring
ΘJC	Thermal Resistance (Junction to Case)		2.5	°C/W
		thermal impedance, per EIA/JESD51.

Capacitance[20]

Parameter	Description	Test Conditions	Max.	Unit
CIN	Input Capacitance	TA = 25°C, f = 1 MHz,	5	pF
		VDD = 2.5V.
CCLK	Clock Input Capacitance		6	pF
		VDDQ = 1.5V
CO	Output Capacitance		7	pF

AC Test Loads and Waveforms

VREF = 0.75V

VREF	0.75V
OUTPUT	Z0 = 50Ω
Device
Under
Test

ZQ

RQ =

250Ω

(a)

RL = 50Ω

VREF = 0.75V

VREF		0.75V	R = 50Ω				[21]
OUTPUT					ALL INPUT PULSES
				1.25V
Device			5 pF 0.25V			0.75V
Under	ZQ				Slew Rate = 2 V/ns
Test		RQ =

250Ω

(b)

Switching Characteristics Over the Operating Range [21]

Cypress

Consortium

167 MHz

Parameter

Parameter

Description

Min.

Max.

Unit

tPower[22]

VCC (typical) to the First Access Read or Write

10

∝s

Cycle Time

tCYC

tKHKH

K Clock and C Clock Cycle Time

6.0

ns

tKH

tKHKL

Input Clock (K/K

and C/C) HIGH

2.4

ns

tKL

tKLKH

Input Clock (K/K

and C/C) LOW

2.4

ns

tKHKH

tKHKH

K/K

Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge

2.7

3.3

ns

to rising edge)

tKHCH

tKHCH

K/K

Clock Rise to C/C Clock Rise (rising edge to rising edge)

0.0

2.0

ns

Set-up Times

tSA

tSA

Address Set-up to Clock (K and

K) Rise

0.7

ns

tSC

tSC

Control Set-up to Clock (K and

K) Rise (RPS, WPS, BWS0, BWS1)

0.7

ns

tSD

tSD

D[17:0] Set-up to Clock (K and

K) Rise

0.7

ns

Hold Times

tHA

tHA

Address Hold after Clock (K and

K) Rise

0.7

ns

tHC

tHC

Control Signals Hold

after

Clock (K and

K) Rise

0.7

ns

(RPS, WPS, BWS0, BWS1)

tHD

tHD

D[17:0] Hold after Clock (K and

K) Rise

0.7

ns

Notes:

20.Tested initially and after any design or process change that may affect these parameters.

21.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250W, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads.

22.This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a read or write operation can be initiated.

Document #: 38-05625 Rev. *A Page 14 of 18

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