Cypress CY7C1365C manual Timing Diagrams, Read Cycle Timing17

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CY7C1365C

Timing Diagrams

Read Cycle Timing[17]

tCYC

CLK

t CH

tADS tADH

ADSP

ADSC

tAS tAH

t CL

tADS tADH

ADDRESS

GW, BWE,BW[A:D]

CE

A1	A2
t WES	tWEH
tCES tCEH	Deselect Cycle
tCES tCEH
	t ADVS tADVH

ADV
OE
		tOEV
		tOEHZ
		tCLZ
Data Out (Q)	High-Z	Q(A1)

tCDV

tOELZ tCDV tDOH

Q(A2) Q(A2 + 1)

ADV suspends burst.

			tCHZ
Q(A2 + 2)	Q(A2 + 3)	Q(A2)	Q(A2 + 1) Q(A2 + 2)
		Burst wraps around

Single READ

to its initial state

BURST

READ

DON’T CARE

UNDEFINED

Note:

17. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05690 Rev. *E

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Contents Selection Guide Functional Description1 Features133 MHz 100 MHz Unit Cypress Semiconductor CorporationCY7C1365C Logic Block Diagram-CY7C1365C 256K x15CY7C1365C Pin ConfigurationsPin Tqfp Pinout 3 Chip Enable a version Tqfp Pin DescriptionsPower supply for the I/O circuitry Power supply inputs to the core of the deviceGround for the core of the device Ground for the I/O circuitryLinear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDFunctional Overview Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsAddress Cycle Description Used Adsp Adsc ADV Write CLKFunction Truth Table for Read/Write3BWE BW D BW C BW B BW a Operating Range Maximum RatingsAmbient Range GND ≤ V I ≤ V DDQAC Test Loads and Waveforms Thermal Resistance10Switching Characteristics Over the Operating Range11 Read Cycle Timing17 Timing DiagramsWrite Cycle Timing18 Read/Write Timing17, 19 Ordering Information ZZ Mode Timing 21DON’T Care Pin Tqfp 14 x 20 x 1.4 mm Package DiagramDocument History Issue Date Orig. Description of ChangeREV ECN no