Cypress CY7C1365C manual Pin Descriptions, Tqfp

CY7C1365C

Pin Descriptions

Name

TQFP

I/O

Description

A0, A1, A

37,36,32,33,34,35,44,45,46,

Input-

Address Inputs used to select one of the 256K address

47,48,49,50,81,82,99,100

Synchronous

locations. Sampled at the rising edge of the CLK if ADSP or

ADSC

92 (for 2 Chip Enable Version)

is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed

43 (for 3 Chip Enable Version)

the 2-bit counter.

A,

B,

93,94,

Input-

Byte Write Select Inputs, active LOW. Qualified with

to

BW

BW

BWE

BWC, BWD

95,96

Synchronous

conduct Byte Writes to the SRAM. Sampled on the rising edge of

CLK.

88

Input-

Global Write Enable Input, active LOW. When asserted LOW on

GW

Synchronous

the rising edge of CLK, a global write is conducted (ALL bytes are

written, regardless of the values on BW[A:D] and BWE).

87

Input-

Byte Write Enable Input, active LOW. Sampled on the rising edge

BWE

Synchronous

of CLK. This signal must be asserted LOW to conduct a Byte Write.

CLK

89

Input-Clock

Clock Input. Used to capture all synchronous inputs to the device.

Also used to increment the burst counter when

ADV

is asserted LOW,

during a burst operation.

1

98

Input-

Chip Enable 1 Input, active LOW. Sampled on the rising edge of

CE

Synchronous

CLK. Used in conjunction with CE2 and CE3 to select/deselect the

device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when

a new external address is loaded.

CE2

97

Input-

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of

Synchronous

CLK. Used in conjunction with CE1 and CE3 to select/deselect the

device. CE2 is sampled only when a new external address is loaded.

3

92 (for 3 Chip Enable Version)

Input-

Chip Enable 3 Input, active LOW. Sampled on the rising edge of

CE

Synchronous

CLK. Used in conjunction with CE1 and CE2 to select/deselect the

device. CE3 is assumed active throughout this document for BGA.

CE3 is sampled only when a new external address is loaded.

86

Input-

Output Enable, asynchronous input, active LOW. Controls the

OE

Asynchronous

direction of the I/O pins. When LOW, the I/O pins behave as outputs.

When deasserted HIGH, I/O pins are tri-stated, and act as input data

pins. OE is masked during the first clock of a Read cycle when

emerging from a deselected state.

83

Input-

Advance Input signal, sampled on the rising edge of CLK. When

ADV

Synchronous

asserted, it automatically increments the address in a burst cycle.

84

Input-

Address Strobe from Processor, sampled on the rising edge of

ADSP

Synchronous

CLK, active LOW. When asserted LOW, addresses presented to the

device are captured in the address registers. A[1:0] are also loaded

into the burst counter. When ADSP and ADSC are both asserted,

only ADSP is recognized. ASDP is ignored when CE1 is deasserted

HIGH.

85

Input-

Address Strobe from Controller, sampled on the rising edge of

ADSC

Synchronous

CLK, active LOW. When asserted LOW, addresses presented to the

device are captured in the address registers. A[1:0] are also loaded

into the burst counter. When ADSP and ADSC are both asserted,

only ADSP is recognized.

ZZ

64

Input-

ZZ “sleep” Input, active HIGH. When asserted HIGH places the

Asynchronous

device in a non-time-critical “sleep” condition with data integrity

preserved. For normal operation, this pin has to be LOW or left

floating. ZZ pin has an internal pull-down.

DQs

52,53,56, 57,58,59, 62,63,68,

I/O-

Bidirectional Data I/O lines. As inputs, they feed into an on-chip

69,72,73,74,75,78,79,2,3,6,7,

Synchronous

data register that is triggered by the rising edge of CLK. As outputs,

8,9,12,13,18,19,22,23,24,25,

they deliver the data contained in the memory location specified by

28,29

the addresses presented during the previous clock rise of the read

cycle. The direction of the pins is controlled by OE. When OE is

asserted LOW, the pins behave as outputs. When HIGH, DQs are

placed in a tri-state condition.

Document #: 38-05690 Rev. *E

Page 5 of 18

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