Cypress CY7C1365C manual Write Cycle Timing18

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CY7C1365C

Timing Diagrams (continued)

Write Cycle Timing[18, 19]

tCYC

CLK

tCH tCL

tADS tADH

ADSP

tADS tADH

ADSC

tAS tAH

ADDRESS A1 A2

Byte write signals are ignored for first cycle when

ADSP initiates burst.

BWE,

BW[A:D]

t t

WES WEH

ADSC extends burst.

tADS tADH

tWES tWEH

tCES tCEH

ADV

Data in (D)

High-Z

Data Out (Q)

tOEHZ

tDS t DH

D(A1)

tADVS tADVH

ADV suspends burst.

D(A2)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

BURST READ

Single WRITE

BURST WRITE

Extended BURST WRITE

DON’T CARE

UNDEFINED

Notes:

18.Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

19.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

Document #: 38-05690 Rev. *E

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Contents 133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description1 Cypress Semiconductor CorporationLogic Block Diagram-CY7C1365C 256K x CY7C1365CPin Configurations 15CY7C1365CPin Tqfp Pinout 3 Chip Enable a version Pin Descriptions TqfpGround for the core of the device Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the I/O circuitryFunctional Overview Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Address Cycle Description Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Adsp Adsc ADV Write CLKBWE BW D BW C BW B BW a Truth Table for Read/Write3Function Ambient Range Maximum RatingsOperating Range GND ≤ V I ≤ V DDQThermal Resistance10 AC Test Loads and WaveformsSwitching Characteristics Over the Operating Range11 Timing Diagrams Read Cycle Timing17Write Cycle Timing18 Read/Write Timing17, 19 DON’T Care ZZ Mode Timing 21Ordering Information Package Diagram Pin Tqfp 14 x 20 x 1.4 mmREV ECN no Issue Date Orig. Description of ChangeDocument History