Cypress manual Logic Block Diagram-CY7C1365C 256K x

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Document #: 38-05690 Rev. *E

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Contents 133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description1 Cypress Semiconductor CorporationLogic Block Diagram-CY7C1365C 256K x CY7C1365CPin Configurations 15CY7C1365CPin Tqfp Pinout 3 Chip Enable a version Pin Descriptions TqfpGround for the core of the device Power supply inputs to the core of the devicePower supply for the I/O circuitry Ground for the I/O circuitryFunctional Overview Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Address Cycle Description Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Adsp Adsc ADV Write CLKBWE BW D BW C BW B BW a Truth Table for Read/Write3Function Ambient Range Maximum RatingsOperating Range GND ≤ V I ≤ V DDQThermal Resistance10 AC Test Loads and WaveformsSwitching Characteristics Over the Operating Range11 Timing Diagrams Read Cycle Timing17Write Cycle Timing18 Read/Write Timing17, 19 DON’T Care ZZ Mode Timing 21Ordering Information Package Diagram Pin Tqfp 14 x 20 x 1.4 mmREV ECN no Issue Date Orig. Description of ChangeDocument History

CY7C1365C