Cypress CY7C1516KV18, CY7C1520KV18 manual Features, Functional Description, Configurations

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CY7C1516KV18, CY7C1527KV18 CY7C1518KV18, CY7C1520KV18

72-Mbit DDR-II SRAM 2-Word Burst Architecture

Features

72-Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

333 MHz Clock for High Bandwidth

2-word Burst for reducing Address Bus Frequency

Double Data Rate (DDR) Interfaces (data transferred at 666 MHz) at 333 MHz

Two Input Clocks (K and K) for precise DDR Timing

SRAM uses rising edges only

Two Input Clocks for Output Data (C and C) to minimize Clock Skew and Flight Time mismatches

Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems

Synchronous Internally Self-timed Writes

DDR-II operates with 1.5 Cycle Read Latency when DOFF is asserted HIGH

Operates similar to DDR-I Device with 1 Cycle Read Latency when DOFF is asserted LOW

1.8V Core Power Supply with HSTL Inputs and Outputs

Variable Drive HSTL Output Buffers

Expanded HSTL Output Voltage (1.4V–VDD)

Supports both 1.5V and 1.8V IO supply

Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)

Offered in both Pb-free and non Pb-free Packages

JTAG 1149.1 compatible Test Access Port

Phase Locked Loop (PLL) for Accurate Data Placement

Functional Description

The CY7C1516KV18, CY7C1527KV18, CY7C1518KV18, and CY7C1520KV18 are 1.8V Synchronous Pipelined SRAM equipped with DDR-II architecture. The DDR-II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1-bit burst counter. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of C and C if provided, or on the rising edge of K and K if C/C are not provided. Each address location is associated with two 8-bit words in the case of CY7C1516KV18 and two 9-bit words in the case of CY7C1527KV18 that burst sequentially into or out of the device. The burst counter always starts with a “0” internally in the case of CY7C1516KV18 and CY7C1527KV18. On CY7C1518KV18 and CY7C1520KV18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of CY7C1518KV18 and two 36-bit words in the case of CY7C1520KV18 sequentially into or out of the device.

Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. Output data clocks (C/C) enable maximum system clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Configurations

CY7C1516KV18 – 8M x 8

CY7C1527KV18 – 8M x 9

CY7C1518KV18 – 4M x 18

CY7C1520KV18 – 2M x 36

Table 1. Selection Guide

Description

 

333 MHz

300 MHz

250 MHz

200 MHz

167 MHz

Unit

Maximum Operating Frequency

 

333

300

250

200

167

MHz

 

 

 

 

 

 

 

 

Maximum Operating Current

x8

510

480

420

370

340

mA

 

 

 

 

 

 

 

 

 

x9

510

480

420

370

340

 

 

 

 

 

 

 

 

 

 

x18

520

490

430

380

340

 

 

 

 

 

 

 

 

 

 

x36

640

600

530

450

400

 

 

 

 

 

 

 

 

 

Cypress Semiconductor Corporation • 198 Champion Court

San Jose, CA 95134-1709

408-943-2600

Document Number: 001-00437 Rev. *E

 

Revised March 30, 2009

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Contents Configurations FeaturesFunctional Description Cypress Semiconductor Corporation 198 Champion CourtLogic Block Diagram CY7C1527KV18 Logic Block Diagram CY7C1516KV18Doff CLKLogic Block Diagram CY7C1520KV18 Logic Block Diagram CY7C1518KV18BWS Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1516KV18 8M x CY7C1527KV18 8M xCY7C1520KV18 2M x CY7C1518KV18 4M xPin Name Pin Description Pin DefinitionsSynchronous Read or Write Input. When Power Supply Inputs for the Outputs of the Device Power supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Programmable Impedance Application ExampleEcho Clocks SRAM#1 ZQOperation Write Cycle DescriptionsFirst Address External Second Address Internal CommentsBWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II SramPLL Constraints VDD/ Vddq DoffDC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Operating RangeAC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitParameter Min Max Switching CharacteristicsPLL Timing Parameter Min Max Output TimesCare Undefined Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History

CY7C1516KV18, CY7C1520KV18, CY7C1527KV18, CY7C1518KV18 specifications

The Cypress CY7C1516KV18, CY7C1520KV18, CY7C1527KV18, and CY7C1518KV18 are a series of high-performance asynchronous static random-access memory (SRAM) devices designed for a variety of applications requiring fast data access and reliable operation. These SRAM chips feature density options ranging from 1Mbit to 4Mbit, catering to a broad spectrum of consumer electronics, telecommunications, networking, and industrial applications.

One of the standout features of these devices is their high-speed access times, which typically range from 12 ns to 15 ns, allowing for rapid data retrieval and writing. This speed makes them ideal for applications where low latency is crucial, such as in cache memory systems and high-speed computing. The low power consumption of these devices also makes them attractive for battery-operated equipment, as they can operate effectively while minimizing energy usage.

The CY7C1516KV18 and other models in this series incorporate advanced CMOS technology, which is instrumental in achieving low standby and active power requirements. This technology not only enhances the overall efficiency of the memory devices but also contributes to reduced thermal generation, which is an essential factor in maintaining performance and longevity in high-density applications.

Data integrity is another critical characteristic of these SRAM devices. They are designed with features such as byte-write capability and asynchronous read/write operations, ensuring that users can manage data efficiently and reliably. The robust architecture also allows for simple interfacing with most processors and microcontrollers, facilitating easy integration into various systems.

The packages of these SRAM chips are available in several form factors, including 44-pin and 48-pin configurations, allowing for flexibility in board design and layout. Their compatibility with standard interface protocols ensures seamless communication with other components of electronic designs.

These Cypress SRAM devices support a range of temperature specifications, making them suitable for both commercial and industrial-grade applications. Enhanced reliability during various operating conditions assures designers that these memory chips will maintain performance in diverse environments.

In summary, the Cypress CY7C1516KV18, CY7C1520KV18, CY7C1527KV18, and CY7C1518KV18 SRAM devices offer high speed, low power consumption, and flexibility in integration. With their advanced technology and robust features, these memory solutions continue to play a vital role in modern electronics, driving innovation across multiple sectors.