Cypress CY7C1518KV18, CY7C1520KV18, CY7C1516KV18 manual Switching Characteristics, Parameter Min Max

Page 23

CY7C1516KV18, CY7C1527KV18

CY7C1518KV18, CY7C1520KV18

Switching Characteristics

Over the Operating Range [20, 21]

 

Cypress

Consortium

 

 

 

 

Description

333 MHz

300 MHz

250 MHz

200 MHz

167 MHz

Unit

Parameter

Parameter

 

 

 

 

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

t

POWER

 

V (Typical) to the First Access [22]

1

–

1

–

1

–

1

–

1

–

ms

 

 

DD

 

 

 

 

 

 

 

 

 

 

 

tCYC

tKHKH

K Clock and C Clock Cycle Time

3.0

8.4

3.3

8.4

4.0

8.4

5.0

8.4

6.0

8.4

ns

tKH

tKHKL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Clock (K/K

and C/C) HIGH

1.20

–

1.32

–

1.6

–

2.0

–

2.4

–

ns

tKL

tKLKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Clock (K/K

and C/C) LOW

1.20

–

1.32

–

1.6

–

2.0

–

2.4

–

ns

tKHKH

tKHKH

K Clock Rise to

 

 

Clock Rise and C

1.35

–

1.49

–

1.8

–

2.2

–

2.7

–

ns

K

 

 

 

to C Rise (rising edge to rising edge)

 

 

 

 

 

 

 

 

 

 

 

tKHCH

tKHCH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K/K

Clock Rise to C/C Clock Rise

0.0

1.30

0.0

1.45

0.0

1.8

0.0

2.2

0.0

2.7

ns

 

 

 

(rising edge to rising edge)

 

 

 

 

 

 

 

 

 

 

 

Setup Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSA

tAVKH

Address Setup to K Clock Rise

0.4

–

0.4

–

0.5

–

0.6

–

0.7

–

ns

tSC

tIVKH

Control Setup to K Clock Rise

0.4

–

0.4

–

0.5

–

0.6

–

0.7

–

ns

 

 

 

(LD, R/W)

 

 

 

 

 

 

 

 

 

 

 

tSCDDR

tIVKH

Double Data Rate Control Setup to

0.3

–

0.3

–

0.35

–

0.4

–

0.5

–

ns

 

 

 

Clock (K/K) Rise

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(BWS0, BWS1,

BWS

2,

BWS

3)

 

 

 

 

 

 

 

 

 

 

 

tSD

tDVKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise

0.3

–

0.3

–

0.35

–

0.4

–

0.5

–

ns

D[X:0] Setup to Clock (K/K)

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tHA

tKHAX

Address Hold after K Clock Rise

0.4

–

0.4

–

0.5

–

0.6

–

0.7

–

ns

tHC

tKHIX

Control

Hold after K Clock Rise

0.4

–

0.4

–

0.5

–

0.6

–

0.7

–

ns

 

 

 

 

 

 

(LD, R/W)

 

 

 

 

 

 

 

 

 

 

 

tHCDDR

tKHIX

Double Data Rate Control Hold after

0.3

–

0.3

–

0.35

–

0.4

–

0.5

–

ns

 

 

 

Clock (K/K) Rise

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(BWS0, BWS1,

BWS

2,

BWS

3)

 

 

 

 

 

 

 

 

 

 

 

tHD

tKHDX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise

0.3

–

0.3

–

0.35

–

0.4

–

0.5

–

ns

D[X:0] Hold after Clock (K/K)

Notes

21.When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated and outputs data with the output timings of that frequency range.

22.This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD min initially before a read or write operation can be initiated.

Document Number: 001-00437 Rev. *E

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesConfigurations Functional DescriptionCLK Logic Block Diagram CY7C1516KV18Logic Block Diagram CY7C1527KV18 DoffBWS Logic Block Diagram CY7C1518KV18Logic Block Diagram CY7C1520KV18 CY7C1527KV18 8M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1516KV18 8M xCY7C1520KV18 2M x CY7C1518KV18 4M xSynchronous Read or Write Input. When Pin DefinitionsPin Name Pin Description TDO for Jtag Power supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Referenced with Respect toFunctional Overview SRAM#1 ZQ Application ExampleProgrammable Impedance Echo ClocksComments Write Cycle DescriptionsOperation First Address External Second Address InternalBWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderVDD/ Vddq Doff Power Up Sequence in DDR-II SramPower Up Sequence PLL ConstraintsOperating Range Electrical CharacteristicsDC Electrical Characteristics Maximum RatingsAC Electrical Characteristics Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max Switching CharacteristicsPLL Timing Parameter Min Max Output TimesCare Undefined Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramDocument History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions

CY7C1516KV18, CY7C1520KV18, CY7C1527KV18, CY7C1518KV18 specifications

The Cypress CY7C1516KV18, CY7C1520KV18, CY7C1527KV18, and CY7C1518KV18 are a series of high-performance asynchronous static random-access memory (SRAM) devices designed for a variety of applications requiring fast data access and reliable operation. These SRAM chips feature density options ranging from 1Mbit to 4Mbit, catering to a broad spectrum of consumer electronics, telecommunications, networking, and industrial applications.

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