Cypress CY7C1520AV18, CY7C1527AV18, CY7C1516AV18, CY7C1518AV18 manual AC Electrical Characteristics

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CY7C1516AV18, CY7C1527AV18

CY7C1518AV18, CY7C1520AV18

Electrical Characteristics (continued)

DC Electrical Characteristics

Over the Operating Range [12]

Parameter	Description	Test Conditions			Min	Typ	Max	Unit
IDD [19]	VDD Operating Supply	VDD = Max,	200MHz	(x8)			700	mA
		IOUT = 0 mA,
		IOUT = 0 mA,		(x9)			700
		f = fMAX = 1/tCYC
		f = fMAX = 1/tCYC		(x18)			700
				(x18)			700

				(x36)			735

			167MHz	(x8)			650	mA

				(x9)			650

				(x18)			650

				(x36)			650

ISB1	Automatic Power down	Max VDD,	300MHz	(x8)			400	mA
	Current	Both Ports Deselected,
	Current	Both Ports Deselected,		(x9)			400
		VIN ≥ VIH or VIN ≤ VIL		(x9)			400

				(x18)			400
		f = fMAX = 1/tCYC, Inputs		(x18)			400
		Static		(x36)			400

			278MHz	(x8)			390	mA

				(x9)			390

				(x18)			390

				(x36)			390

			250MHz	(x8)			380	mA

				(x9)			380

				(x18)			380

				(x36)			380

			200MHz	(x8)			360	mA

				(x9)			360

				(x18)			360

				(x36)			360

			167MHz	(x8)			340	mA

				(x9)			340

				(x18)			340

				(x36)			340

AC Electrical Characteristics

Over the Operating Range [11]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VIH

VIL

Input HIGH Voltage		VREF + 0.2	–	–	V
Input LOW Voltage		–	–	VREF – 0.2	V

Document Number: 001-06982 Rev. *D

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1527AV18 Logic Block Diagram CY7C1516AV18Doff CLKLogic Block Diagram CY7C1518AV18 Logic Block Diagram CY7C1520AV18BWS Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1516AV18 8M x CY7C1527AV18 8M xCY7C1520AV18 2M x CY7C1518AV18 4M xPin Definitions Pin Name Pin DescriptionSynchronous Read or Write input. When Power Supply Inputs for the Outputs of the Device Power supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagSingle Clock Mode Functional OverviewDDR Operation Depth Expansion Application ExampleProgrammable Impedance Echo ClocksOperation Write Cycle DescriptionsFirst Address External Second Address Internal BWS0/ BWS1 NWS0 NWS1BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics DLL Timing Static to DLL ResetNOP Switching WaveformsRead NOP Write ReadOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsREV ECN no Submission ORIG. Description of Change Date