Cypress CY7C1518AV18, CY7C1527AV18, CY7C1520AV18, CY7C1516AV18 manual Switching Characteristics

Page 23

CY7C1516AV18, CY7C1527AV18

CY7C1518AV18, CY7C1520AV18

Switching Characteristics

Over the Operating Range [20, 21]

 

Cypress

Consortium

 

 

 

 

Description

300 MHz

278 MHz

250 MHz

200 MHz

167 MHz

Unit

Parameter

Parameter

 

 

 

 

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

t

POWER

 

V (Typical) to the First Access [22]

1

–

1

–

1

–

1

–

1

–

ms

 

 

DD

 

 

 

 

 

 

 

 

 

 

 

tCYC

tKHKH

K Clock and C Clock Cycle Time

3.3

8.4

3.6

8.4

4.0

8.4

5.0

8.4

6.0

8.4

ns

tKH

tKHKL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Clock (K/K

and C/C) HIGH

1.32

–

1.4

–

1.6

–

2.0

–

2.4

–

ns

tKL

tKLKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Clock (K/K

and C/C) LOW

1.32

–

1.4

–

1.6

–

2.0

–

2.4

–

ns

tKHKH

tKHKH

K Clock Rise to

 

 

Clock Rise and C

1.49

–

1.6

–

1.8

–

2.2

–

2.7

–

ns

K

 

 

 

to C Rise (rising edge to rising edge)

 

 

 

 

 

 

 

 

 

 

 

tKHCH

tKHCH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K/K

Clock Rise to C/C Clock Rise

0.0

1.45

0.0

1.55

0.0

1.8

0.0

2.2

0.0

2.7

ns

 

 

 

(rising edge to rising edge)

 

 

 

 

 

 

 

 

 

 

 

Setup Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSA

tAVKH

Address Setup to K Clock Rise

0.4

–

0.4

–

0.5

–

0.6

–

0.7

–

ns

tSC

tIVKH

Control Setup to K Clock Rise

0.4

–

0.4

–

0.5

–

0.6

–

0.7

–

ns

 

 

 

(LD, R/W)

 

 

 

 

 

 

 

 

 

 

 

tSCDDR

tIVKH

Double Data Rate Control Setup to

0.3

–

0.3

–

0.35

–

0.4

–

0.5

–

ns

 

 

 

Clock (K/K) Rise

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(BWS0, BWS1,

BWS

2,

BWS

3)

 

 

 

 

 

 

 

 

 

 

 

tSD [23]

tDVKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise

0.3

–

0.3

–

0.35

–

0.4

–

0.5

–

ns

D[X:0] Setup to Clock (K/K)

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tHA

tKHAX

Address Hold after K Clock Rise

0.4

–

0.4

–

0.5

–

0.6

–

0.7

–

ns

tHC

tKHIX

Control

Hold after K Clock Rise

0.4

–

0.4

–

0.5

–

0.6

–

0.7

–

ns

 

 

 

 

 

 

(LD, R/W)

 

 

 

 

 

 

 

 

 

 

 

tHCDDR

tKHIX

Double Data Rate Control Hold after

0.3

–

0.3

–

0.35

–

0.4

–

0.5

–

ns

 

 

 

Clock (K/K) Rise

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(BWS0, BWS1,

BWS

2,

BWS

3)

 

 

 

 

 

 

 

 

 

 

 

tHD

tKHDX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise

0.3

–

0.3

–

0.35

–

0.4

–

0.5

–

ns

D[X:0] Hold after Clock (K/K)

Notes

21.When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range.

22.This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD min initially before a read or write operation can be initiated.

23.For DQ0 data signal on CY7C1527AV18 device, tSD is 0.5 ns for 200 MHz, 250 MHz, 278 MHz and 300 MHz frequencies.

Document Number: 001-06982 Rev. *D

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Contents Selection Guide FeaturesConfigurations Functional DescriptionCLK Logic Block Diagram CY7C1516AV18Logic Block Diagram CY7C1527AV18 DoffBWS Logic Block Diagram CY7C1518AV18Logic Block Diagram CY7C1520AV18 CY7C1527AV18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1516AV18 8M xCY7C1520AV18 2M x CY7C1518AV18 4M xSynchronous Read or Write input. When Pin DefinitionsPin Name Pin Description TCK Pin for Jtag Power supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagDDR Operation Single Clock ModeFunctional Overview Echo Clocks Application ExampleDepth Expansion Programmable ImpedanceBWS0/ BWS1 NWS0 NWS1 Write Cycle DescriptionsOperation First Address External Second Address InternalBWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TCK TAP Controller Block DiagramTAP Electrical Characteristics TDITAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitSwitching Characteristics DLL Timing Static to DLL ResetNOP Write Read Switching WaveformsNOP ReadOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramREV ECN no Submission ORIG. Description of Change Date Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions
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