Cypress CY7C1520AV18, CY7C1527AV18, CY7C1516AV18 manual Package Diagram, Ball Fbga 15 x 17 x 1.4 mm

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CY7C1516AV18, CY7C1527AV18

CY7C1518AV18, CY7C1520AV18

Package Diagram

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Document Number: 001-06982 Rev. *D

Page 29 of 30

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1527AV18 Logic Block Diagram CY7C1516AV18Doff CLKBWS Logic Block Diagram CY7C1518AV18Logic Block Diagram CY7C1520AV18 Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1516AV18 8M x CY7C1527AV18 8M xCY7C1520AV18 2M x CY7C1518AV18 4M xSynchronous Read or Write input. When Pin DefinitionsPin Name Pin Description Power Supply Inputs for the Outputs of the Device Power supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagDDR Operation Single Clock ModeFunctional Overview Depth Expansion Application ExampleProgrammable Impedance Echo ClocksOperation Write Cycle DescriptionsFirst Address External Second Address Internal BWS0/ BWS1 NWS0 NWS1BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics DLL Timing Static to DLL ResetNOP Switching WaveformsRead NOP Write ReadOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramREV ECN no Submission ORIG. Description of Change Date Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions