Cypress CY7C144 manual 8K x9 Dual-Port Sram, Pin Plastic Leaded Chip Carrier CY7C145-35JXC

Page 18

CY7C145, CY7C144

8K x9 Dual-Port SRAM

Speed

Ordering Code

Package

Package Type

Operating

(ns)

Name

Range

15

CY7C145-15AC

A80

80-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C145-15AXC

A80

80-Pin Pb-Free Thin Quad Flat Pack

 

 

 

 

 

 

 

CY7C145-15JC

J81

68-Pin Plastic Leaded Chip Carrier

 

 

 

 

 

 

25

CY7C145-25AC

A80

80-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C145-25JC

J81

68-Pin Plastic Leaded Chip Carrier

 

 

 

 

 

 

 

CY7C145-25AI

A80

80-Pin Thin Quad Flat Pack

Industrial

 

 

 

 

 

 

CY7C145-25JI

J81

68-Pin Plastic Leaded Chip Carrier

 

 

 

 

 

 

35

CY7C145-35AC

A80

80-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C145-35JC

J81

68-Pin Plastic Leaded Chip Carrier

 

 

 

 

 

 

 

CY7C145-35JXC

J81

68-Pin Pb-Free Plastic Leaded Chip Carrier

 

 

 

 

 

 

 

CY7C145-35AI

A80

80-Pin Thin Quad Flat Pack

Industrial

 

 

 

 

 

 

CY7C145-35JI

J81

68-Pin Plastic Leaded Chip Carrier

 

 

 

 

 

 

55

CY7C145-55AC

A80

80-Pin Thin Quad Flat Pack

Commercial

 

 

 

 

 

 

CY7C145-55JC

J81

68-Pin Plastic Leaded Chip Carrier

 

 

 

 

 

 

 

CY7C145-55AI

A80

80-Pin Thin Quad Flat Pack

Industrial

 

 

 

 

 

 

CY7C145-55JI

J81

68-Pin Plastic Leaded Chip Carrier

 

 

 

 

 

 

Document #: 38-06034 Rev. *D

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Contents
Functional Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion CourtPin Configurations Pin Plcc Top ViewPin Definitions Left Port Right Port Description Selection Guide DescriptionUnit Electrical Characteristics Over the Operating Range Maximum RatingsOperating Range Capacitance Parameter Description Test Conditions Max UnitSwitching Characteristics Over the Operating Range9 7C144-35 7C144-55 Parameter Description 7C145-15 Switching Characteristics Over the Operating Range7C144-15 7C145-35 7C145-55 Unit MinSwitching Waveforms Read Cycle No Either Port Address Access15CY7C145, CY7C144 Semaphore Read After Write Timing, Either Side25 Read with Busy M/S=HIGH20 CER Valid First Right Address Valid FirstRight Side Sets INT L Left Side Sets INT RRight Side Clears INT R Left Side Clears Intl Architecture Interrupt Operation Example assumes = High Non-Contending Read/Write Inputs OutputsOperation Function Left Port Right PortTypical DC and AC Characteristics Pin Plastic Leaded Chip Carrier CY7C144-15JXC Ordering Information8K x8 Dual-Port Sram Pin Plastic Leaded Chip Carrier CY7C144-55JXC8K x9 Dual-Port Sram Pin Plastic Leaded Chip Carrier CY7C145-35JXCPackage Diagrams Pin Thin Plastic Quad Flat Pack 14 x 14 x 1.4 mm A65Pin Thin Plastic Quad Flat Pack A80 Sales, Solutions and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History
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