Cypress CY7C144, CY7C145 manual Architecture

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CY7C145, CY7C144

Architecture

The CY7C144/5 consists of a an array of 8K words of 8/9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes or reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be used for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the CY7C144/5 can function as a Master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The CY7C144/5 has an automatic power down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device.

Functional Description

Write Operation

Data must be set up for a duration of tSD before the rising edge of R/W to guarantee a valid write. A write operation is controlled by either the OE pin (see Figure 8 on page 9) or the R/W pin (see Write Cycle No. 2 waveform). Data can be written to the device tHZOE after the OE is deasserted or tHZWE after the falling edge of R/W. Required inputs for non-contention operations are summarized in Table 3.

If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must be met before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port.

Read Operation

When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE are asserted. If the user of the CY7C144/5 wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin.

Interrupts

The interrupt flag (INT) permits communications between ports.When the left port writes to location 1FFF, the right port’s interrupt flag (INTR) is set. This flag is cleared when the right port reads that same location. Setting the left port’s interrupt flag (INTL) is accomplished when the right port writes to location 1FFE. This flag is cleared when the left port reads location 1FFE. The message at 1FFF or 1FFE is user-defined. See Table 4 for input requirements for INT. INTR and INTL are push-pull outputs and do not require pull-up resistors to operate.

Busy

The CY7C144/5 provides on-chip arbitration to alleviate simul- taneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other the Busy logic determines which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not guaranteed which one. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. BUSYL and BUSYR in master mode are push-pull outputs and do not require pull-up resistors to operate.

Master/Slave

An M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This enables the device to interface to a master device with no external components.Writing of slave devices must be delayed until after the BUSY input has settled. Otherwise, the slave chip may begin a write cycle during a contention situation.When presented a HIGH input, the M/S pin allows the device to be used as a master and therefore the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave.

Semaphore Operation

The CY7C144/5 provides eight semaphore latches which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a 0 to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value is available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a 0), it assumes control over the shared resource, otherwise (reads a 1) it assumes the right port has control and continues to poll the semaphore.When the right side has relin- quished control of the semaphore (by writing a 1), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a 1 is written to cancel its request.

Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip enable for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2represents the semaphore address. OE and R/W are used in the same manner as a normal memory access.When writing or reading a semaphore, the other address pins have no effect.

When writing to the semaphore, only I/O0 is used. If a 0 is written to the left port of an unused semaphore, a 1 appears at the same semaphore address on the right port. That semaphore can now only be modified by the side showing 0 (the left port in this case). If the left port now relinquishes control by writing a 1 to the semaphore, the semaphore will be set to 1 for both sides. However, if the right port had requested the semaphore (written a 0) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 5 shows sample semaphore operations.

When reading a semaphore, all eight/nine data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore.

Initialization of the semaphore is not automatic and must be reset during initialization program at power up. All Semaphores on both sides should have a one written into them at initialization from both sides to assure that they are free when needed.

Document #: 38-06034 Rev. *D

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Contents Functional Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion CourtPin Configurations Pin Plcc Top ViewUnit Pin Definitions Left Port Right Port DescriptionSelection Guide Description Operating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Capacitance Parameter Description Test Conditions Max UnitSwitching Characteristics Over the Operating Range9 7C144-35 7C144-55 Parameter Description 7C145-15 Switching Characteristics Over the Operating Range7C144-15 7C145-35 7C145-55 Unit MinSwitching Waveforms Read Cycle No Either Port Address Access15CY7C145, CY7C144 Semaphore Read After Write Timing, Either Side25 Read with Busy M/S=HIGH20 CER Valid First Right Address Valid FirstRight Side Sets INT L Left Side Sets INT RRight Side Clears INT R Left Side Clears IntlArchitecture Interrupt Operation Example assumes = High Non-Contending Read/Write Inputs OutputsOperation Function Left Port Right PortTypical DC and AC Characteristics Pin Plastic Leaded Chip Carrier CY7C144-15JXC Ordering Information8K x8 Dual-Port Sram Pin Plastic Leaded Chip Carrier CY7C144-55JXC8K x9 Dual-Port Sram Pin Plastic Leaded Chip Carrier CY7C145-35JXCPackage Diagrams Pin Thin Plastic Quad Flat Pack 14 x 14 x 1.4 mm A65Pin Thin Plastic Quad Flat Pack A80 Document History Sales, Solutions and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions

CY7C145, CY7C144 specifications

Cypress Semiconductor is renowned for its advanced memory solutions, and two of its noteworthy products are the CY7C144 and CY7C145, both of which serve as emerging leaders in the field of synchronous dynamic random-access memory (SDRAM). These memory chips provide high-speed data access, making them ideal for various applications, including networking, automotive, and industrial electronics.

The CY7C144 is a 4-Mbit SRAM, while its counterpart, the CY7C145, is an 8-Mbit SRAM. Both chips utilize a synchronous interface, which allows them to operate at clock rates that significantly enhance data retrieval speeds. Designed for low power consumption, these devices feature several power-saving modes, making them suitable for battery-operated applications.

One of the main features of the CY7C144 and CY7C145 is their support for burst read and write operations. This function enables the memory to deliver multiple bits of data sequentially with a single command, substantially increasing throughput. Additionally, both models come with a wide data bus, typically 16 bits, allowing for efficient data handling and alignment with a variety of systems.

The technology behind these chips includes static CMOS processes, which promote high performance and reliability under various operating environments. The CY7C144 and CY7C145 both guarantee a high level of data integrity, thanks to advanced error detection and correction features. This makes them especially valuable in applications where data accuracy is critical.

Another critical aspect is the integration of an on-chip address decoder for efficient memory addressing, minimizing delays during data access. This characteristic plays a crucial role in optimizing the overall system performance, particularly in high-bandwidth applications.

In terms of environmental resilience, these memories are designed to withstand a range of temperatures, making them robust enough for industrial applications. The CY7C144 and CY7C145 also comply with several industry standards, ensuring compatibility with a wide array of devices and systems.

In summary, the CY7C144 and CY7C145 by Cypress Semiconductor stand out due to their blend of high speed, low power consumption, and robust reliability. With advanced features like burst read/write capabilities, error detection, and temperature resilience, these memory chips are exceptional choices for modern electronic applications demanding speed and efficiency. Their continued evolution reflects Cypress's commitment to innovation in the semiconductor industry, catering to the growing needs of a data-driven world.
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