Cypress CY7C144, CY7C145 manual CER Valid First, Right Address Valid First

Page 12

CY7C145, CY7C144

Switching Waveforms (continued)

Figure 14. Busy Timing Diagram No. 1 (CE Arbitration)[29]

CEL Valid First:

ADDRESSL,R

CEL

CER

BUSYR

ADDRESS MATCH

 

tPS

 

tBLC

tBHC

CER Valid First:

ADDRESSL,R

CER

CEL

BUSYL

ADDRESS MATCH

 

tPS

 

tBLC

tBHC

Figure 15. Busy Timing Diagram No. 2 (Address Arbitration)[29]

Left Address Valid First:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADDRESSL

 

 

 

 

 

 

 

 

 

 

 

tRC or tWC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADDRESS MATCH

 

 

 

 

ADDRESS MISMATCH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADDRESSR

 

 

 

 

 

 

 

 

tPS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tBLA

 

 

 

 

 

 

 

tBHA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUSY

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Right Address Valid First:

ADDRESSR

ADDRESSL

BUSYL

tRC or tWC

ADDRESS MATCH

 

ADDRESS MISMATCH

 

tPS

 

 

tBLA

 

 

 

 

 

 

 

tBHA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note:

29. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted

Document #: 38-06034 Rev. *D

Page 12 of 21

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Image 12 Contents
Features Logic Block DiagramFunctional Description Cypress Semiconductor Corporation 198 Champion CourtPin Configurations Pin Plcc Top ViewPin Definitions Left Port Right Port Description Selection Guide DescriptionUnit Electrical Characteristics Over the Operating Range Maximum RatingsOperating Range Capacitance Parameter Description Test Conditions Max UnitSwitching Characteristics Over the Operating Range9 Switching Characteristics Over the Operating Range 7C144-157C144-35 7C144-55 Parameter Description 7C145-15 7C145-35 7C145-55 Unit Min Switching Waveforms Read Cycle No Either Port Address Access15CY7C145, CY7C144 Semaphore Read After Write Timing, Either Side25 Read with Busy M/S=HIGH20 CER Valid First Right Address Valid FirstLeft Side Sets INT R Right Side Clears INT RRight Side Sets INT L Left Side Clears IntlArchitecture Non-Contending Read/Write Inputs Outputs OperationInterrupt Operation Example assumes = High Function Left Port Right PortTypical DC and AC Characteristics Ordering Information 8K x8 Dual-Port SramPin Plastic Leaded Chip Carrier CY7C144-15JXC Pin Plastic Leaded Chip Carrier CY7C144-55JXC8K x9 Dual-Port Sram Pin Plastic Leaded Chip Carrier CY7C145-35JXCPackage Diagrams Pin Thin Plastic Quad Flat Pack 14 x 14 x 1.4 mm A65Pin Thin Plastic Quad Flat Pack A80 Sales, Solutions and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History