Cypress CY7C145, CY7C144 manual Switching Characteristics Over the Operating Range, 7C144-15

CY7C145, CY7C144

Switching Characteristics Over the Operating Range[9]												(continued)
										7C144-15		7C144-25		7C144-35		7C144-55
Parameter					Description					7C145-15		7C145-25		7C145-35		7C145-55		Unit
										Min	Max	Min	Max	Min	Max	Min	Max
tSD		Data Set-Up to Write End								10		15		15		25		ns
tHD		Data Hold From Write End								0		0		0		0		ns
tHZWE[11,12]		R/W		LOW to High Z							10		15		20		25	ns
tLZWE[11,12]		R/W		HIGH to Low Z						3		3		3		3		ns
tWDD[13]		Write Pulse to Data Delay									30		50		60		70	ns
tDDD[13]		Write Data Valid to Read Data									25		30		35		40	ns
		Valid
BUSY TIMING[14]
tBLA		BUSY			LOW from Address						15		20		20		30	ns
		Match
tBHA		BUSY			HIGH from Address						15		20		20		30	ns
		Mismatch
tBLC		BUSY			LOW from	CE		LOW			15		20		20		30	ns
tBHC		BUSY			HIGH from		CE	HIGH			15		20		20		30	ns
tPS		Port Set-Up for Priority								5		5		5		5		ns
tWB		R/W		LOW after BUSY LOW						0		0		0		0		ns
tWH		R/W		HIGH after BUSY HIGH						13		20		30		30		ns
tBDD		BUSY			HIGH to Data Valid						15		25		35		55	ns
INTERRUPT TIMING[14]
tINS		INT	Set Time								15		25		25		35	ns
tINR		INT	Reset Time								15		25		25		35	ns
SEMAPHORE	TIMING
tSOP		SEM Flag Update Pulse							(OE	10		10		15		20		ns
		or SEM)
tSWRD		SEM Flag Write to Read Time								5		5		5		5		ns
tSPS		SEM Flag Contention								5		5		5		5		ns
		Window

Notes

13.For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.

14.Test conditions used are Load 2.

Document #: 38-06034 Rev. *D Page 7 of 21

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