Cypress CY7C1344H manual Timing Diagrams, Read Cycle Timing16, Clk, Adsc, DON’T Care

Page 10

CY7C1344H

Timing Diagrams

tCYC

t CH

tADS tADH

t CL

ADSP

tADS tADH

tAS tAH

ADDRESS

GW, BWE,BW[A:D]

tCDV

tOELZ tCDV tDOH

Q(A2) Q(A2 + 1)

ADV suspends burst.

Single READ

to its initial state

BURST

READ

UNDEFINED

Note:

16. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 001-00211 Rev. *B

Page 10 of 15

[+] Feedback

Image 10

Contents Logic Block Diagram Functional Description1 FeaturesCypress Semiconductor Corporation 15CY7C1344H Pin ConfigurationsSelection Guide 133 MHz 100 MHz UnitPin Definitions Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDFunctional Overview Address Cycle Description Used ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Adsp Adsc ADV Write CLKFunction Truth Table for Read/Write2BWE BW D BW C BW B BW a Ambient Range Maximum RatingsOperating Range Description Test Conditions Min Max UnitThermal Resistance9 Capacitance9AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 10 CLK Timing DiagramsRead Cycle Timing16 AdscWrite Cycle Timing16 Address Read/Write Timing16, 18Adsp Adsc Burst ReadZZ Mode Timing 20 DON’T CareOrdering Information Package DiagramPin Tqfp 14 x 20 x 1.4 mm REV ECN no Issue Date Orig. Description of ChangeDocument History PCI