
CY7C1344H
Timing Diagrams (continued)
Write Cycle Timing[16, 17]
tCYC
CLK
tCH tCL
tADS tADH
ADSP
tADS tADH
ADSC
tAS tAH
ADDRESS A1
A2
Byte write signals are ignored for first cycle when
ADSP initiates burst.
BWE,
BW[A:D]
t t
WES WEH
ADSC extends burst.
tADS tADH
A3
tWES tWEH
GW
tCES tCEH
CE
ADV
OE
Data in (D) |
Data Out (Q)
tOEHZ
tDS t DH
D(A1)
tADVS tADVH
ADV suspends burst.
D(A2) | D(A2 + 1) | D(A2 + 1) | D(A2 + 2) | D(A2 + 3) | D(A3) | D(A3 + 1) | D(A3 + 2) |
BURST READ
Single WRITE | BURST WRITE | Extended BURST WRITE |
DON’T CARE | UNDEFINED |
Note:
17. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.
Document #: | Page 11 of 15 |
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