Cypress CY7C1344H manual Write Cycle Timing16

Cypress CY7C1344H manual Features, Logic Block Diagram Functional Description1, Cypress Semiconductor Corporation
Cypress manual Selection Guide, Pin Configurations, 15CY7C1344H, MHz 100 MHz Unit
Cypress CY7C1344H manual Pin Definitions
Cypress CY7C1344H manual Functional Overview, Interleaved Burst Address Table Mode = Floating or VDD
Cypress CY7C1344H manual ZZ Mode Electrical Characteristics, Parameter Description Test Conditions Min Max Unit
Cypress CY7C1344H manual Truth Table for Read/Write2, Function, BWE BW D BW C BW B BW a
Cypress CY7C1344H manual Maximum Ratings, Operating Range, Ambient Range, Description Test Conditions Min Max Unit
Cypress CY7C1344H manual Capacitance9, Thermal Resistance9, AC Test Loads and Waveforms
Cypress CY7C1344H manual Switching Characteristics Over the Operating Range 10
Cypress CY7C1344H manual Timing Diagrams, Read Cycle Timing16, Clk, Adsc, DON’T Care
Cypress CY7C1344H manual Write Cycle Timing16
Cypress CY7C1344H manual Read/Write Timing16, 18, Adsp Adsc, Address, Burst Read, DON’T Care Undefined
Cypress CY7C1344H manual ZZ Mode Timing 20, DON’T Care
Cypress CY7C1344H manual Ordering Information, Package Diagram, Pin Tqfp 14 x 20 x 1.4 mm
Cypress CY7C1344H manual Document History, REV ECN no, Issue Date Orig. Description of Change, Pci, Nxr
Page 11

CY7C1344H

Timing Diagrams (continued)

Write Cycle Timing[16, 17]

tCYC

CLK

tCH tCL

tADS tADH

ADSP

tADS tADH

ADSC

tAS tAH

ADDRESS A1 A2

Byte write signals are ignored for first cycle when

ADSP initiates burst.

BWE,

BW[A:D]

t t

WES WEH

ADSC extends burst.

tADS tADH

A3

tWES tWEH

GW

tCES tCEH

CE

ADV

OE

Data in (D)

High-Z

Data Out (Q)

tOEHZ

tDS t DH

D(A1)

tADVS tADVH

ADV suspends burst.

D(A2)

D(A2 + 1)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

BURST READ

Single WRITE

BURST WRITE

Extended BURST WRITE

DON’T CARE

UNDEFINED

Note:

17. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

Document #: 001-00211 Rev. *B

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram Functional Description1 133 MHz 100 MHz Unit Pin ConfigurationsSelection Guide 15CY7C1344HPin Definitions Functional Overview Interleaved Burst Address Table Mode = Floating or VDDLinear Burst Address Table Mode = GND Adsp Adsc ADV Write CLK ZZ Mode Electrical CharacteristicsParameter Description Test Conditions Min Max Unit Address Cycle Description UsedBWE BW D BW C BW B BW a Truth Table for Read/Write2Function Description Test Conditions Min Max Unit Maximum RatingsOperating Range Ambient RangeAC Test Loads and Waveforms Capacitance9Thermal Resistance9 Switching Characteristics Over the Operating Range 10 Adsc Timing DiagramsRead Cycle Timing16 CLKWrite Cycle Timing16 Burst Read Read/Write Timing16, 18Adsp Adsc AddressDON’T Care ZZ Mode Timing 20Pin Tqfp 14 x 20 x 1.4 mm Package DiagramOrdering Information PCI Issue Date Orig. Description of ChangeDocument History REV ECN no
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