Cypress CY7C1344H manual Maximum Ratings, Operating Range, Ambient Range, Gnd ≤ V I ≤ V Ddq

CY7C1344H

Maximum Ratings

(Above which the useful life may be impaired. For user guide- lines, not tested.)

Storage Temperature		–65°C to +150°C
Ambient Temperature with
Power Applied		–55°C to +125°C
Supply Voltage on VDD Relative to GND		–0.5V to +4.6V
Supply Voltage on VDDQ Relative to GND		–0.5V to +VDD
DC Voltage Applied to Outputs
in Tri-State	–0.5V to VDDQ + 0.5V

Electrical Characteristics Over the Operating Range [7, 8]

DC Input Voltage		–0.5V to VDD + 0.5V
Current into Outputs (LOW)			20 mA
Static Discharge Voltage			> 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current			> 200 mA
Operating Range
	Ambient
Range	Temperature]	VDD	VDDQ
Commercial	0°C to +70°C	3.3V −5%/+10%	2.5V –5%
			to VDD
Industrial	–40°C to +85°C

Parameter	Description	Test Conditions		Min.	Max.	Unit
VDD	Power Supply Voltage			3.135	3.6	V
VDDQ	I/O Supply Voltage	for 3.3V I/O		3.135	VDD	V
		for 2.5V I/O		2.375	2.625	V
VOH	Output HIGH Voltage	for 3.3V I/O, IOH = –4.0 mA		2.4		V
		for 2.5V I/O, IOH = –1.0 mA		2.0
VOL	Output LOW Voltage	for 3.3V I/O, IOL = 8.0 mA			0.4	V
		for 2.5V I/O, IOL = 1.0 mA			0.4
VIH	Input HIGH Voltage[7]	for 3.3V I/O		2.0	VDD + 0.3V	V
		for 2.5V I/O		1.7	VDD + 0.3V
VIL	Input LOW Voltage[7]	for 3.3V I/O		–0.3	0.8	V
		for 2.5V I/O		–0.3	0.7
IX	Input Leakage Current	GND ≤ VI ≤ VDDQ		−5	5	µA
	except ZZ and MODE
	Input Current of MODE	Input = VSS		–30		µA
		Input = VDD			5	µA
	Input Current of ZZ	Input = VSS		–5		µA
		Input = VDD			30	µA
IOZ	Output Leakage Current	GND ≤ VI ≤ VDDQ, Output Disabled		–5	5	µA
IDD	VDD Operating Supply	VDD = Max., IOUT = 0 mA,	7.5-ns cycle, 133 MHz		225	mA
	Current	f = fMAX= 1/tCYC
			10-ns cycle, 100 MHz		205	mA
ISB1	Automatic CE Power-Down	Max. VDD, Device Deselected,	7.5-ns cycle, 133 MHz		90	mA
	Current—TTL Inputs	VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
			10-ns cycle, 100 MHz		80	mA
		inputs switching
ISB2	Automatic CE Power-Down	Max. VDD, Device Deselected,	All speeds		40	mA
	Current—CMOS Inputs	VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
		f = 0, inputs static
ISB3	Automatic CE Power-Down	Max. VDD, Device Deselected,	7.5-ns cycle, 133 MHz		75	mA
	Current—CMOS Inputs	VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V,
			10-ns cycle, 100 MHz		65	mA
		f = fMAX, inputs switching
ISB4	Automatic CE Power-Down	Max. VDD, Device Deselected,	All speeds		45	mA
	Current—TTL Inputs	VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
		f = 0, inputs static

Notes:

7.Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).

8.TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

Document #: 001-00211 Rev. *B Page 7 of 15

[+] Feedback