Cypress CY7C1344H manual ZZ Mode Timing 20, DON’T Care

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CY7C1344H

ZZMode Timing [20, 21]

t ZZ

t ZZI

ISUPPLY

I DDZZ

ALL INPUTS (except ZZ)

Outputs (Q)

High-Z

t ZZREC

t RZZI

DESELECT or READ Only

Notes:

20.Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

21.DQs are in High-Z when exiting ZZ sleep mode.

Document #: 001-00211 Rev. *B

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Contents Logic Block Diagram Functional Description1 FeaturesCypress Semiconductor Corporation Selection Guide Pin Configurations15CY7C1344H 133 MHz 100 MHz UnitPin Definitions Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDFunctional Overview Parameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsAddress Cycle Description Used Adsp Adsc ADV Write CLKFunction Truth Table for Read/Write2BWE BW D BW C BW B BW a Operating Range Maximum RatingsAmbient Range Description Test Conditions Min Max UnitThermal Resistance9 Capacitance9AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 10 Read Cycle Timing16 Timing DiagramsCLK AdscWrite Cycle Timing16 Adsp Adsc Read/Write Timing16, 18Address Burst ReadDON’T Care ZZ Mode Timing 20Ordering Information Package DiagramPin Tqfp 14 x 20 x 1.4 mm Document History Issue Date Orig. Description of ChangeREV ECN no PCI