CY7C1344H
Switching Characteristics Over the Operating Range [10, 11]
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| 133 MHz | 100 MHz |
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Parameter |
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| Description |
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| Unit |
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| Min. | Max. | Min. | Max. | |||
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t |
| V (Typical) to the First Access[12] | 1 |
| 1 |
| ms | ||||||||||
POWER |
| DD |
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Clock |
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tCYC |
| Clock Cycle Time | 7.5 |
| 10 |
| ns | ||||||||||
tCH |
| Clock HIGH | 2.5 |
| 4.0 |
| ns | ||||||||||
tCL |
| Clock LOW | 2.5 |
| 4.0 |
| ns | ||||||||||
Output Times |
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tCDV |
| Data Output Valid after CLK Rise |
| 6.5 |
| 8.0 | ns | ||||||||||
tDOH |
| Data Output Hold after CLK Rise | 2.0 |
| 2.0 |
| ns | ||||||||||
tCLZ |
| Clock to | 0 |
| 0 |
| ns | ||||||||||
tCHZ |
| Clock to |
| 3.5 |
| 3.5 | ns | ||||||||||
tOEV |
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| LOW to Output Valid |
| 3.5 |
| 3.5 | ns | ||||||||
OE |
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tOELZ |
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| LOW to Output | 0 |
| 0 |
| ns | ||||||||
OE |
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tOEHZ |
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| HIGH to Output |
| 3.5 |
| 3.5 | ns | ||||||||
OE |
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tAS |
| Address | 1.5 |
| 2.0 |
| ns | ||||||||||
tADS |
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| 1.5 |
| 2.0 |
| ns | ||
ADSP, | ADSC |
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tADVS |
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| 1.5 |
| 2.0 |
| ns | |||||||
ADV |
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tWES |
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| [A:D] | 1.5 |
| 2.0 |
| ns | |
GW, | BWE, | BW |
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tDS |
| Data Input | 1.5 |
| 2.0 |
| ns | ||||||||||
tCES |
| Chip Enable | 1.5 |
| 2.0 |
| ns | ||||||||||
Hold Times |
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tAH |
| Address Hold after CLK Rise | 0.5 |
| 0.5 |
| ns | ||||||||||
tADH |
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| Hold after CLK Rise | 0.5 |
| 0.5 |
| ns | |
ADSP, | ADSC |
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tWEH |
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| [A:D] Hold after CLK Rise | 0.5 |
| 0.5 |
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GW, | BWE, | BW |
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tADVH |
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| Hold after CLK Rise | 0.5 |
| 0.5 |
| ns | |||||||
ADV |
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tDH |
| Data Input Hold after CLK Rise | 0.5 |
| 0.5 |
| ns | ||||||||||
tCEH |
| Chip Enable Hold after CLK Rise | 0.5 |
| 0.5 |
| ns |
Notes:
10.Timing reference level is 1.5V when VDDQ = 3.3V and 1.25V when VDDQ = 2.5V.
11.Test conditions shown in (a) of AC Test Loads unless otherwise noted.
12.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation can be initiated.
13.tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from
14.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
15.This parameter is sampled and not 100% tested.
Document #: | Page 9 of 15 |
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