Cypress CY7C1344H Read/Write Timing16, 18, Adsp Adsc, Address, Burst Read, DON’T Care Undefined

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CY7C1344H

Read/Write Timing[16, 18, 19]

tCYC

CH CL

tADS tADH

tAS tAH

Notes:

18.The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

19.GW is HIGH.

A5 A6

D(A5) D(A6)

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Document #: 001-00211 Rev. *B

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Contents Features Logic Block Diagram Functional Description1Cypress Semiconductor Corporation Pin Configurations Selection Guide15CY7C1344H 133 MHz 100 MHz UnitPin Definitions Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDFunctional Overview ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitAddress Cycle Description Used Adsp Adsc ADV Write CLKTruth Table for Read/Write2 FunctionBWE BW D BW C BW B BW a Maximum Ratings Operating RangeAmbient Range Description Test Conditions Min Max UnitCapacitance9 Thermal Resistance9AC Test Loads and Waveforms Switching Characteristics Over the Operating Range 10 Timing Diagrams Read Cycle Timing16CLK AdscWrite Cycle Timing16 Read/Write Timing16, 18 Adsp AdscAddress Burst ReadZZ Mode Timing 20 DON’T CarePackage Diagram Ordering InformationPin Tqfp 14 x 20 x 1.4 mm Issue Date Orig. Description of Change Document HistoryREV ECN no PCI